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Recent content by nashafi

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    Question about the clock of the FIR pipeline delay

    Re: fir design I am designing the same thing. How are you taking care of coefficients like 0.000034567 in an HDL language. Thanks, -Nauman
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    Using Generate statements in my RTL?

    I second this lat comment. But it depends what you are actually designing. If its a DSP application like an FIR etc , it will take a lot of time to write the code and generate saves you from that at the cost of area at the least.
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    FPGA board for begineers

    I am using XESS corporation boards with Xilinx webpack and they are working pretty good. Their range is big starting from as cheap as $50. www.xess.com -Nauman
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    How to use multiple clocks in a VHDL based data path?

    vhdl multiple clocks Hi, I am designing a decimation filter for a data standard like ardis or mobitex. since there is a lot of upsampling and downsampling going on so i need multiple clocks all the way in my pipeline. How can i write different clocks for my test bench. I am confused about how...
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    which synthesis tool are you using?

    Presision RTL for FPGA CAdence ENcounter for ASIC and AMBIT
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    How to use floating point coefficients in an FIR using VHDL?

    Re: How to use floating point coefficients in an FIR using V Can any one convert this one 0.00029044 what will be a suitable multiplication factor ? if i have to shift left then still it is floating point ? can i define integer := 0.00029044 in VHDL or i have to convert it to binary to...
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    How to use floating point coefficients in an FIR using VHDL?

    Hi, I am writing an FIR filter in VHDL and i tested with some random coefficients like 1,2,3,4,5 and it works fine for impulse response. Now I have to test it with some actual coefficients which are like -0.00000001234 or 0.0000234569 I was wondering that if some one can tell me how to...
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    Cadence ambit and Encounter tutorial

    cadence ambit Hi, i am looking for some tutorials for Cadence tools ambit and encounter. I would appreciate if any one can post a link here. Thanks, -Nauman
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    How to compile Xilinx core MAC unit?

    Re: xilinx core.. help! just check if the core is targetted to ISE version you are using. I used the PCI core once and only major problem i got into was that the core was targetted to ISE version 5.1 and i was using 6.1. other then that i dont remember having any problems. good luck
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    Looking for beginner resources about VHDL programming

    Re: vhdl programming this is what i used to learn VHDL . Downloaded and installed mentro Graphics model sim from xilinx website ( its free and the one of the best HDL simulators around) . then bought two books The beginners guide to VHDL by P J Ashenden and The designers guide to VHDL by P J...
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    How to make my VHDL core protected or make an IP-Core?

    Hi, I have designed a MAP deocder architecture flow here at my research group. I am now exploring the option of giving it for commercial use. But i have no clue as how i can protect my VHDL code and still give some one some thign which they can use to target any FPGA platform or may be change...
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    How can I make my own ip core ?

    Can some one further specify that how to distribute an IP core written in VHDL without realy giving away the VHDL code?
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    how u deign memory in verlog

    Any memory would require a memory definition and an address decoder. Regrardless of you use an HDL or design a circuit. et's say for example in VHDL (as i use it more then Verilog) you need to define the width and length of memory using a 2-D array style and then write a counter which counts all...
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    Information about microcontroller programming

    Re: microcontroller If you have been working with any aspects of electronics before and just want to explore micro controllers now then just go to any micro controller manual. to start with use either PIC or ATmel's micro controllers. I have used ATMEL AT89C2051 for small scale projects. it has...
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    Thesis on Reconfigurable computing, any help !!

    if you are interested in cryptography then you can choose like AES and then look for all possible architecture ideas in IEEE research journals and then come up with your own implementation of a customized architecture and then improve the performance by any ecided parameter either of area ...
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