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Re: Post layout extraction
It depends on your rule file support R/C extraction or not.
In DIVA, if you has rule file that support R/C extraction, you can extract R/C by setting switches in Extractor windows (click Set Switches and select resistor option). There will be a presistor and...
gds scale uu/dbu
Before importing, you should have standard cells layout in CIW that have name correspond to you LEF in SE.
When you Import->Stream, add option retain library definition.
This option will search the cell name in CIW that match with the cell name from SE and use that cell in CIW...
Hi Gian,
It is very interesting acticle but the file is damage.
I don't know is it comes from my network or your uploaded file.
Could you please check the uploaded file or re-upload the new one?
Thank you very much.
site:www.edaboard.com skill cdsinit
I thought you have file A.il in the same directory you excecute icfb. Make sure that you load skill with full path, load("{FULLPATH}/A.il") not only load("A.il")
Hope it could solve your problem.
I use CMOS process. But I made a diode from PMOS with drain-gate connected so my diode is in a Nwell and I connected Nwell to VDD.
For substrate, I also connected to GND.
Sorry for my wrong information.
napong.
Hi,
Usually I connect the substrate to the VDD after rectification. But the substrate junction which normally reversed will be forworded at each peak of AC input. So try to make AC peak to VDD drop as small as possible to make small forwarded substrate junction and check your substrate current...
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