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The phase accuracy is limited to 18bit only for avoid to wait for long time simulation in debug phase (in which am I), the target is 48bit for phase accumulator and probably 18bit for the DAC.
Thank for the tips ... I have read yet something about CORDIC alg. and Taylor series approach....
I...
Hi all,
I have elaborate the simulation results obtainated after then I wired the phase accumulator with the ROM (that contain the wave values) and the results not appear affetct by any form of spurs (naturally is present quantization error).
I attach the results:
Hi all,
I have a question about a phase accumulator that I'm doing for implement a DDS in an ATLYS board (SPARTAN6).
The phase accumulator that I wrote works with a input 18bit phase_word_width and outputs a 10bit address to a RAM block.
When I set a phase word that set integer or fractional...
Correct, I add that this aspect of VHDL is called OVERLOAD. This is a mechanism which permit to define more functions with the same name, the use of each function is based on the operand check (or "context" as alexan_e as mentioned). Then in VHDL exist more of one function called "<=". For...
Hi all,
I have some questions about the timing control of signals hsync & vsync in an hdmi-tx.
I read an old post about the use of these signals but nothing about their duration or "duty-cycle" therefore I write this thread.
How sayed in other thread, the hsync is the signal for tell to reciever...
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