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vhdl FIR
after your correction, are you getting the desired outcome?
depending on the precision you want as well as where the "decimal point" in on your input sample, COEF and desired output are, you might need to shift your output appropriately.
paths on SDF should match your verilog model's specify block.
you can try generating SDF without conditional path in case your specify block does not have COND statements.
vhdl FIR
Cannot remember my VHDL now and the data types so I'll assume this is allowed ;-)
signal result_int: integer range -32767 to 32767;
signal sum_int: integer range -2147483647 to 2147483647;
However, how does this translate?
result_int <= sum_int;
Don't you want to shift...
Did you miss 1 port in regmux on you latest version?
module regmux(r,d,ena,clk,rst);
has 5 ports. you used to have 6. also on the instantiation of regmux, it has 6 too...
regmux register0(reg_out[0],reg_out[0],data[0],ena,clk,rst);
you might want to fix that and see if that is your problem.
help on ATPG ATE test!
There are a number of possible causes. A lot of these stem out of timing relationships between flops. Since you have managed to pass 35 patterns, we can assume timing for shifting is no problem. So if there is any timing problems, it will have to be on the capture cycle...
i agree with sudhirkv.
but the fundamental issue here is the difference between
#10 clk = ~clk;
and
clk = #10 ~clk;
if you've usedthe former, then it does not matter where the initial block is, while the latter, as you've realized is more sensitive to it. i suggest you use the former for...
SDRAM controller
it seems like you've kept your CAS always asserted thru the burst read and write... i'd suggest you de-assert cas after fsm_read and fsm_write1.
need some info
yes it is possible. you might need to have an external USB PHY. xilinx and altera have fpga big enough to implemet the full usb 2.0 controller.
another thing you might want to look at is quicklogic (a smaller fpga company) has a chip with built-in usb controller including phy...
working of counter in state machines
you could always choose to use 3 separate counters to do 3 separate delays. it will be cleaner but more expensive in terms of gates.
or you could share. one way is by doing a decrement instead of increment, this way all the end state is the same (which is...
oh... of course... what i meant was to replace
a <= a1 or a2;
b <= b1 or b2;
with
a <= (a1 and clk) or (a2 and not clk);
b <= (b1 and clk) or (b2 and not clk);
while keeping the rest of the code (the 2 processes) to model double edge flops as the former will not.
i will suggest
a <= (a1 and clk) or (a2 and not clk);
b <= (b1 and clk) or (b2 and not clk);
just like what i assume a double edged flop will do it.. a mux after the 2 flops.
again, i imagine a1 and b1 always being 1 and a2 b2 always being 0 makes little sense... actually, if this were true...
ok, yeah you did have 2 ns on the input delay... so once your simulation testbench matches this (i.e. all inputs come out 2ns after clock edge) then your sims should match your STA freq closely.
verilog synthesis problem
can you check the testbench you are using to run the sims. the module that is "driving" the signals... those should have "correct" delay wrt the clocks else you are going to have some timing problems. if it is too little you will have hold problems, too much, setup...
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