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Re: centroid matching
The first one is preferred, because the axis of symmetry is in between the B's where ABBA is divided into 2 mirror image halves (AB - BA). However, dummies must be placed on each end of A's, coz the segments of this device occupy both ends of the array.
Hi,
I have also experience these errors when i use "path" to create 45deg-angles signal lines. Now to avoid this error, i just use "rectangle" and "polygon" to create the shapes. My minor grids are set to 0.01, so when i check the properties of the shape created and when the co-ordinates show 3...
Re: IC Design And Layout
Hi,
For IC layout, these books are recommended:
IC Layout Basics : A Practical Guide
by Christopher Saint, Judy Saint
h**p://
The Art of Analog Layout
by Alan Hastings
h**p://
If there are critical signal lines running across both Vdd and Gnd (if they are bound to cross), what are the methods used to decrease the noise coupling of the signal lines?
Re: ESD
Hi,
These books offer the required information on ESD protection:
On-Chip ESD Protection for IC - An IC Design Perspective
by Albert Z. H. Wang
h**p://
Basic ESD and I/O Design
by Sanjay Dabral, Timothy Maloney
You can also search on the internet for:
ming-dou ker
The author has...
Re: drawing circuits
I normally use OrCad to draw it, and then copy paste it to the report. It looks nice and neat (that is, if there's ample of time to draw it). A faster way to do it is probably what sengyee88 has suggested... to make it look much nicer after inverting the colours, there's...
Re: MOS orientation
It is true that in some cases, the orientation of the MOS transistor may not be the same due to constraints in space and wiring length. However, in my layouts, i'd try to orientate them in the same direction where-ever possible...unless, it takes up too much space or too...
Yes, depending on what metal layer you use for the Vdd/Vss, the respective metal current density should be followed. The design manual would contain the information or formulas for you to calculate the minimum width, but if more space is available, then the metal layer could be made wider.
Hi ssankurathri,
If i am not mistaken, the foundry's documents would have the information or formulas that relate the metal layers to their respective current densities...
In my layouts, the width (instead of length) of the metal were made to withstand the required current. For example, from...
Re: analog layout
Hi,
Although IC layout is different from PCB layout, it is not too difficult to learn. However, care must be taken when doing the analog IC layout, as the analog portion of the IC layout have more considerations compared to digital portions. There are several good books for...
hi, analog_v and rghrob,
maybe u can try to ask a friend/colleague who has an EDAboard forum account to log in and see if the link works, coz sometimes, i find that certain login can have access to the links, and certain login just don't have the access...
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