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I found the problem, in the line
assign i_Tx_DV = finish_ps2 & can_call;
This causes some kind of bug, when I change it to
assign i_Tx_DV = finish_ps2;
It works! can_call is a physical switch located on the board.
Hello,
Recently I made a verilog project that uses two Altera DE2-115 FPGA to communicate with each other, when I type in a keyboard connected to the "A" FPGA it shows on the LCD of the "B" FPGA.
My problem is that the code was working just fine, but for some reason when I tested it today it...
Hello,
I'm trying to create a "messaging interface" between two FPGA using the UART protocol to communicate between one another, the goal is to type some text into a keyboard connected via PS/2 to one FPGA and have the message appear in the other FPGA's LCD. So far I have the PS/2...
Yes, if I don't use a clock divider the timing requirements are not met, and the setup slack becomes really low (somewhere around -120). Currently my patch solution is to use a clock divider, but my understanding is that it's not a good idea, how can I find places that most affect the timing?
As...
Hello,
I'm designing a 32bit CPU as a recurring assignment for my university classes. Currently it can run a single program, the next step is to make it run multiple programs preemptively, with the help of a "operating system" that would overseer the other running programs.
The problem is that...
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