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Hi,
in a new design with Zynq UltraScale+ MPSoC we have to switch from our old firmware, written with XilKernel in Virtex 5 / Artix-7, to a freeRTOS kernel.
I create a sample project with the freeRTOS hello world and network echo server. In main routine I can't find routines for kernel...
Hi,
I'm looking for a VHDL core which calculates a CRC for 16-Bit Datawords. Can you tell me where I can find something?
Thank you for your help.
BR
martin
Hello,
at the moment I implement my first design with aurora core. According to the manual I have to wait during clock synchronization time:
What will happen on the receiver side during the clock sync? Will the received data also hold?
Thank you for your help.
BR
martin sauer
Hi,
in our design (Artix-7 200) I use an Aurora 8B10B core with the following parameters:
I expect a tx_out_clk rate of 100MHz but it seems that isn't it. What is the correct clock rate?
Thank you for your help.
BR
martin
Hi all,
this is my first design with an Aurora 8B/10B core, so I have problems to bring up the core. My device ist an Artix-7 200 TFBG676 and the Serdes Lines are connected to a SFP fibre optic modul.
I create the core with Vivado 2019.1.3 IP wizard and place the Serdes Lines at X0Y0. In my...
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