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Hi,
There is no library for DDC in either Xilinx ISE or Matlab. DDC is any application, you have to make this application by comprising all different modules according your need.
If you are following GSM standards, there is a demo available "GSM DOWNCOVERTER" in Simulink. It is also...
Hi
1. IEEE.std_logic_1164 is general purpose library for all VHDL code. In ISE installation, you can find a programme called "Xilinx Core Generator". It generates IPs. You can configure many parameters for any components. NCO, Multipliers, FIRs are available. Once you finish with the...
Hi,
One month as a beginner is extremely difficult to implement this task.
1. Do one thing, instead of writing your VHDL code, use IP cores readily available in Xilinx ISE. You can find cores for FIR, CIC, DDS/NCO/DCO.
2. RF frequency does not matter now. You transferred it to IF. Tell me IF...
Hi,
It is a fundamental thing of communications engineering. You need to read a book on basics of digital communications. And another thing is that each down converter is custom made for particular frequency requirement. So source codes from others work may not help you on first hand. If not...
Yes, I know that CDMA has been implemented on FPGA but I meant to say that doing alone as a project is very lengthy and tough task.
Well, one suggestion. Start with implementing Simulink model. There are lot of examples on CDMA. It is the best way to elaborate the design. You will get lot of...
Hi,
I worked for Digital Communications on FPGA but never designed anything for audio processing algorithms. I would like to capture audio signals, usually from Microphone, into digital format and process them for converting into digital sequence like PCM-NRZ. I have heard about...
Spartan 3 has Microblaze processor (32 bit). Also, you can insert 3rd party soft processors like ARM Cortex. You will required Xilinx Platform Studio to write soft code and make HW/SW design.
By the way, C/C++ is very easy to implement on FPGA but not sure about Java.
complete CDMA system on FPGA as a project is impossible. You can implement some part of it. Also, you need to do lot of verification and system level design in other ESL softwares. e.g MATLAB, SystemC or others.
Addition: Are you planning to implement only CDMA algorithm (e.g. PN sequence and...
You need external oscillator (Crystal) to generate source clock. 100 MHz oscillator is available.
If you want to generate from other clock frequency then use FPGA's inbuilt PLL/DCM.
If you want to generate for the simulation purpose, use time command in your testbench.
hope it helps
Two options:
Option 1: For Altera FPGAs, you can use DSP Builder and design complete digital system within Simulink.
Option 2: Use Simulink blocks and build the filter and generate HDL from the Simulin model. It is an automatic process but consider the fact that only some of the Simulink...
Hi,
The code written above can not be synthesized. But there is a solution. You need to use two different processes, one at positive edge and other at negative edge. After your processes finish you need to write a logic to select your signals and transfer the value to the output.
Please read...
Try to make Simulink model from your algorithm and then replace it using System Generator blocks. It is better to have Simulink model in any case of dealing with hardware design.
If your algorithm is written in .m files then use Xilinx AccelDSP. I developed signal processing algorithms and...
Re: DC-DC down converter
Hi Tahmid,
But this circuit may not work at high current. I need to design to measure the voltage at very high current level, ranging from 1 A to 25 A.
Thanks
Mukesh
Re: DC-DC down converter
Hi Tahmid,
Actually I want to measure the voltage level of the DC source using electronics circuit but at such high voltage electronics does not work. Therefore, I want to decrease the voltage level to 5V or 3.3 V. If the DC source voltage is lower, the output of my...
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