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Morell

Recent content by Morell

VHDL exercise : 256Bytes RAM

WOW!!!!! Thanks alot!!! I will consider a way to reset the RAM - - - Updated - - - @Matrixofdynamism I'm Trying to reset the RAM, But I don't know how to reset a 2D signal!!! Is there command for this type of operation?
- Morell
- Post #3
- Nov 25, 2016
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
VHDL exercise : 256Bytes RAM

Hi everybody I want to design a 256x8 Memory (RAM) and this is my code: entity RAM_256Bytes is Port ( CLK : in STD_LOGIC; R_W : in STD_LOGIC; -- 1 means READ, 0 means WRITE Address : in STD_LOGIC_VECTOR (7 downto 0); Din : in STD_LOGIC_VECTOR (7 downto...
- Morell
- Thread
- Nov 25, 2016
- Replies: 12
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Microsemi, Microprocessor subsystems

Microsemi, Microcontroller subsystems Hi guys I want to have a presentation about microsemi MSS and I don't know where to start. where can I find answers to the following questions: 1- What is the concept of MSS? 2- What are the advantages and disadvantages of MSS? 3- I want to compare a...
- Morell
- Post #6
- Nov 13, 2016
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Microsemi, Microprocessor subsystems

Thanks alot So we call the hardcore processor or the software processor a "Microprocessor subsystem", is that right?
- Morell
- Post #3
- Nov 6, 2016
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Microsemi, Microprocessor subsystems

Hi everybody I want to start a research about "Microsemi Microprocessor subsystems" and I don't even know where should I look for this title. - I've looked for it in Microsemi.com But the Microprocessor field was empy. - I've googled "Microsemi microprocessor subsystems" and "Microprocessor...
- Morell
- Thread
- Nov 6, 2016
- Replies: 6
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Pure Combinational ALU (Tasks : Add,Mul and Sub)

1- Re: I dont know anything about these librarys, I just saw an example and put that there. right now, if i remove std_logic_unsigned, does it work? if it doesn't, what is your suggestion 2- Re: Again, Examples, If I use signed or unsigned instead of...
- Morell
- Post #3
- Jun 4, 2016
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Pure Combinational ALU (Tasks : Add,Mul and Sub)

Hi everyone I need help with writhing this combinational ALU Here is my code library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity PocketCalculator is Generic (Bits : integer := 8); Port ( Input_1 : in STD_LOGIC_VECTOR (Bits-1 downto 0):=(Others...
- Morell
- Thread
- Jun 4, 2016
- Replies: 4
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Does ISE Design suite works on Linux?

Hi I want to install ISE Design suite 14.7 on a linux os and I have five questions. 1- Does it work? If the answer is "yes", 2- Please tell the name of that linux os (ubunto or ...) And if it's "no" , 3- Does ise have a linux version? 4- What's it's name (For example ISEX...
- Morell
- Thread
- Jan 18, 2016
- Replies: 1
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Debouncer & FIFO in VHDL

Transmitter & Debouncer in VHDL Hi, I designed 3 modules with your help, All of them worked on the board. But there was a small problem in testing the code on the board (Spartan-3 50Mhz). 1- These are the codes : - Top module entity Transmitter_Test is Generic ( FIFO_Length...
- Morell
- Post #8
- Jan 1, 2016
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
FIFO and Serial Transmitter in VHDL

Hi Guys I need your help again. :-) Here is the Scenario of what I want to do : 1- I have and input that is std_logic_vector (N downto 0) and 5<N<31. N is a Generic. 2- I want to send this input (5 to 31 bits) with my serial transmitter. I am going to Discribe that I plan to do, if...
- Morell
- Thread
- Dec 30, 2015
- Replies: 2
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Debouncer & FIFO in VHDL

Re: Debouncer & FIFO in VHDL @Ads-ee Thank you very much I didn't quite understand the "Debouncer" part but I will think about it. About the FIFO. That is not really a FIFO. :-D FIFO has to work as I Discribe: 1- The top module in which FIFO is used, sends 1 to 4 (FIFO_Length) bytes...
- Morell
- Post #5
- Dec 29, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Debouncer & FIFO in VHDL

Yes this is possible. What should I do? This is exactly what my teacher said. I have no idea what to do.
- Morell
- Post #3
- Dec 29, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
Debouncer & FIFO in VHDL

Hi, I wrote these Components. I simulated both of them and they worked correctly but in implementation(Spartan-3 50MHz), they sometimes work and sometimes don't. 1- Debouncer: There are two counters : Clock_Divider_Counter (Works with 50MHz) and Debounce_Counter (Works with 1KHz) If...
- Morell
- Thread
- Dec 29, 2015
- Replies: 7
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Systematic Cyclic Encoder in VHDL

Hi Guys, Thanks alot for your help, It all Worked pretty well, :-)
- Morell
- Post #45
- Dec 18, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
[SOLVED] Serial Receiver & transmitter in VHDL

Thanks alot for your response!! That is exactly what I am looking for. I will write the new transmitter with your advises and tips.
- Morell
- Post #6
- Dec 17, 2015
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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Morell

Welcome to EDAboard.com

Recent content by Morell

VHDL exercise : 256Bytes RAM

VHDL exercise : 256Bytes RAM

Microsemi, Microprocessor subsystems

Microsemi, Microprocessor subsystems

Microsemi, Microprocessor subsystems

Pure Combinational ALU (Tasks : Add,Mul and Sub)

Pure Combinational ALU (Tasks : Add,Mul and Sub)

Does ISE Design suite works on Linux?

Debouncer & FIFO in VHDL

FIFO and Serial Transmitter in VHDL

Debouncer & FIFO in VHDL

Debouncer & FIFO in VHDL

Debouncer & FIFO in VHDL

[SOLVED] Systematic Cyclic Encoder in VHDL

[SOLVED] Serial Receiver & transmitter in VHDL

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