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Recent content by mordak

  1. M

    [Moved]: Dynamic range of amplifiers

    Re: Dynamic range of amplifiers Hi Klaus Thanks for your comment. To answer to your question " How fair is a comparison of a 1kHz with an 1GHz amplifier anyway?" I should say I made an exaggeration to make a point. Say you and I are in charge of designing an opamp, you design one with 2 kHz...
  2. M

    [Moved]: Dynamic range of amplifiers

    Hi all, I am a bit confused about dynamic range of amplifiers. Based on my understanding, dynamic range is defined as the ratio of the maximum signal the amplifier can deliver over its total noise. Now here is the problem, if you have an amplifier that has a low bandwidth, say 1 kHz, it may...
  3. M

    Analog filter delay time

    Thanks everyone for contributing in this thread, especially SunnySkyguy, LvW and FvM. I didn't get your phase delay equation. Can you send me the ref you get this equation from. You mentioned phase shift can be a propagation delay, but they do not have the same unit (degree vs second). I'm...
  4. M

    Analog filter delay time

    Thanks all for the responses. I really appreciate your help. Do you know any ref that formulates these relationships? I think the propagation delay is related to the filter order. There is also slewing in the figure I posted and I think it comes from the opamp used in the filter, actually...
  5. M

    Analog filter delay time

    Thanks for the comments. I included a figure form an online article about filters: I am interested in both propagation delay and settling time, but mostly propagation delay. Let's say you have a sine wave that at the time t=0 you apply the signal to the circuit. The output of the filter at...
  6. M

    Analog filter delay time

    Thanks Audioguru for your reply. Would you mind sending me a ref that has those equations? I am aware that say a first order low-pass filter needs some time based on its time constant to settle properly. However, I am looking for a quantitative way to figure out the propagation delay and...
  7. M

    Analog filter delay time

    Hi, I am trying to design an analog low pass filter. I was wondering if there is any equation showing the relation between the filter spec, say order of the filter, and its settling time and propagation delay. And if there is any, will it depend on the filter topology? Any help is appreciated...
  8. M

    Source of distortion in ADCs

    Hi, I have a couple of question about distortion and non-linearities in ADCs. I wonder except INL and DNL that cause distortion in ADCS, what can cause a bad THD. Assume someone wants to model the distortion in an ADC, say third order harmonic. I wonder if the extra term added to the pure...
  9. M

    Symmetric non overlapping clock generator

    Attached is the power spectrum of the system, it is a converter and as you can see there is a distortion at Fs - Fin, close to 47.5 MHz that is merely due to the asymmetric non overlapping clocks I mentioned before.
  10. M

    Symmetric non overlapping clock generator

    Tnx for all the comments. The attached is an example of what I want. There are a couple of things I need to describe: I need to have non-overlapping clocks and dead zone, or duty cycle do not matter that much to me. What I have noticed in my simulations was that any mismatch between pulse...
  11. M

    Symmetric non overlapping clock generator

    Thanks for your comment! I use a NOCG like the one attached. The input clock is 100 MHz and W0 and W1 are connected to bunch of inverters. So I would say W0 and W1 would see a load of like 100 fF (both non overlapping clocks have an equal load to drive). I noticed that there is 500 ps time...
  12. M

    Symmetric non overlapping clock generator

    Hi, Implementing a non overlapping clock generator (NOCG) is fairly straightforward. But my problem is that the generated non-overlapped clocks are not symmetric (On time of the two non-overlapped clocks is slightly different). I read somewhere that adding an asymmetric transmission gate will...
  13. M

    Generating delayed clock (frequency dependent)

    Re: Generating delayed clock (frequnecy dependent) It's varying from 15 MHz to 150 MHz, with 10 steps. It's just a small digital part of a big mixed-mode circuit, which I prefer to avoid using any complex circuit. So I hope there would be a way to do it without using a PLL.
  14. M

    Generating delayed clock (frequency dependent)

    Generating delayed clock (frequnecy dependent) Hi, I was trying to make a delay version of a clock signal which is, say 1/5th of the period delayed compared to the original signal. If I generate this delayed clock with chain of inverter gates, that would work. However, if I change the the...
  15. M

    Storing a ramp signal voltage at a random time

    Thanks guys for your comments. I try to avoid sample and hold, not only because it increases complexity, it also can't save the voltage for a long time since parasitic will discharge the sampling cap. Unless there is any dynamic analog voltage refreshing approach (don't know if that exists) it...
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