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hi
i am writing code for mux in verilog using UDP.
compilation is ok.
when i do simulation then this gives error like that -
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: C:/modeltech_6.5/examples/verilogpermitive.v(17): Internal error: ../../../src/vlog/vtree_inline.c(1587)...
hi
as we write
library ieee;
use ieee.std_logic_1164.all;
in vhdl for including library.
what we write in verilog to include library...............
I am writing same but didnt work....
any one suggest me............
hi
i m designin four quadrent analog multiplier. the topology which i choose is given in fig.
i designed symatic and the designed circuit give correct output for input dynamic range -1 V to 1V.
i designe the circuit in voltage mode. but one of my frnd say it is current mode circuit. and he say...
hi
i m designin four quadrent analog multiplier. the topology which i choose is given in fig.
i designed symatic and the designed circuit give correct output for input dynamic range -1 V to 1V.
i designe the circuit in voltage mode. but one of my frnd say it is current mode circuit. and he say...
Can u tell what is the diffrence between current mode and voltage mode circuits?. And where I get some materials about the current mode circuit.For what purpose we do current mode designing?
hi
i m designing 4 quadrent analog multiplier. there r four ip terminal in my strecture.
i m giving V1+v1, V1-v1, V2+v2, V2-v2, signal at the input terninals, where V is D.C. bias and v is analog signal. i m gettin correct out put.but i dont know how can i do a.c. analisis of the circuit. i mean...
when we apply a increasing voltage over the gate of n mos transistor then at a perticular voltage transistor is on i.e. channel is formed between drain and source.
For formation of channel from where these electron come. i mean they come from bulk or source. if they come from bulk then on...
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