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Recent content by mohaddin

  1. M

    Latch and Flip-Flop as a sequential circuit

    Latch and Flip-Flop Hi Latch is a level sensitive, but FF is a edge triggered. regards Moha
  2. M

    Materials for practicing timing analysis and fsms

    Timing Analysis Hi salma please send it yaar Regards Mohi
  3. M

    Engineering Change Order

    Hi Good explanation man Regadsr Mohi baba
  4. M

    how to minimize the interconnect while doing synthesis?

    Hi u r waste fellow, how metals come into picture in Logic synthesis. Regards Mohi
  5. M

    Effect of MultiCycle Paths on timing

    Hi spartanthewarrior Yes man its good link Regadrs Mohi
  6. M

    Synthesis--> Generic cell library

    Hi Please refer DC manual for this Regards Mohi
  7. M

    How to avoid clock,signal and reset violations when doing scan insertion?

    Scan Insertion Hi Good man Lucky me Regards Mohi baba
  8. M

    Powerpoint presentation of Static Timing Analysis

    Static Timing Analysis Hi sandeep Good ppt man Thanks from all of us Regards Mohi baba
  9. M

    Do the cell libraries used for synthesis contain comparators

    Comparator standard cell Hi Usually in std cell libraries u dont find comparators, multipliers, carrylookadder etc, if u r using design complier, then synopsys will provide these components with the dc tool, interms of designware components. Regards Mohi
  10. M

    useful timing analysis article

    Hi amnsgk Yes its really good ppt for timing analysis. Regards Mohi
  11. M

    Blocking and Non-Blocking assignment

    xilinx blocking vs non blocking Hi Alll Just go through verilog Basics by salman palnitkar, its good book for verilog basics. regards Mohi
  12. M

    Differences between the layout in Custom Design and Semi-Custom Design

    LAYOUT Hi Semicustom design means, u will make use of Std cell libraries for ASIC design. Reagrds Mohi
  13. M

    how to understand set_output_delay ?

    Hi Just go through Design Complier manual man u will understand everything Regards Mohi
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