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Hi All,
Kindly can anyone explain to me why we need to limit the max fanout of all inputs to be 1
e.g. "set_max_fanout 1 [all_inputs]"
my understanding is that the max fanout should be constraind output pins only so why we constraint the max fanout of primary input ports?
Thanks in advance
Hi all,
i want to generate the sync signals (Vsync & Hsync) to a CHRONTEL dvi transmitter device CH7301C via vhdl
i can generate it to interface VGA is there is a difference between Hsync & Vsync at VGA vs. DVI?
thanks in advance
There is a group called PADS ASCII STD BD Outlines that you should be able to import.
The files are in PADS V5 format and will need to be translated up to V9.0
File > Import > ASCII
Also, there are these PCIe Cards for both the short and long versions -
PCIeV36
PCIeV64
PCIeV98
PCIeV164
pads9.0 pin group
Hi all,
it's my first time to work on pads9.0.
- what's the function of pin group and what's the difference between Gate-A pin vs signal pin vs unused pin?
- if i choose Gate-A pin group what's the difference between all of it's types?
thanks in advance
xilinx core generator
i try to implement the vhdl file but i've this error
"The design is empty. No processing will be done"
could u please provide me with some tutorials?!
xilinx core generator
Hi all
i use xilinx core generator to generate floating point adder now i generate the core but i don't know how to implement it.
can anyone help me .
thanks in advance
what's this error?!
Thanks all,
i found a solution for this error i have to use the latest version of the ModelSim since that the Spartan-6 FPGA released 2009
Hi Farhada
i read this guide but it seems that it's talk about the functionality of the DSP slice .
i need to know how to use it in adder/subtractor,and multiplication using VHDL could you plz support me with some VHDL tutorials & examples?!
thanks in advance
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