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You can do in a lot of way.
1) Simpler (but it depends of AD interface) you can give the clock directly to the AD and it has on its output port DATA, VALID and a CLK with which you can acquire correctly the data.
2) If it's not your case, the only solution is to have 1 CLK reference that go in a...
At the moment I live in Italy, but I would like to relocate in order to make new experiences and improve my technical knowledge, maybe exploring new applications.
I'm 33y.o. and I work in digital electronic since 2001.
I've a strong background in FPGA and VHDL other than all basic things that a...
Have you an idea of what is VHDL?
I mean it's not a tool to write software, but you've to figure out what you wanna do in HW (register, chip select, data routing, clock, etc..).
need help guys
I don't know if maxplus can do that.
Quartus II surely can and can also import your Maxplus2 code, so switch to quartus II, import your project and convert it from there.
Clock to Pad Timing?
Imo you've to really understand what are theese values.
I mean:
Period is 5ns because your clk runs to 200Mhz and that's ok
Pad to setup and clk to pad are the timing you've to define in order to have hold and setup time that are ok with your external speification if pad...
Imo a well written book usefull to people that at the end have to implement thing and don't bother too much on maths behind is:
"Richard G. Lyons
Understanding Digital Signal Processing
Prentice Halls"
That's very nice expecially about the filters part (and tricks about them and DFT).
For the...
It's not so difficult as you can image.
Start to design your electric schematic and than regoup the pin into the FPGA by function.
In FPGA you'll simply have to design the protocol of communications that your sensor need in order to read the data.
Or if you've simply a bus with the data going...
No way, it's not so symply thing..
I suggest you to start read some good book about it in order to divide your digital modulation in sub-block. There are also some basis thesis on the net that you can find about this arguments.
Moreover it's better to focus directly on the kind of modulation...
If your A signal is bigger than a clock cycle, it's really better that you reveal it's rising edge synchronously (yes you'll have 2 clk of delay, but usually it's not a problem) and use this generated sygnal as an enable in your synchronous design.
Done that, you'll have that your code will be...
vhdl reverse bits
Can't you simply declare them as in reverse order?
I mean in VHDL I can declare a signal as:
a : std_logic_vector (7 downto 0);
but then I can use it also in reverse order writing:
a(0 downto 7) <= x"01";
that will be interpreted as I've written:
a(7 downto 0) <= x"80";
but...
If WR and RD are the command of the processor and address it's address bus a simple address decoding is something like this:
write_uart <= ((address = UART_ADDRESS) and (WR='1') and (RD='0'));
read_uart <= ((address = UART_ADDRESS) and (WR='0') and (RD='1'));
To pipeline correctly your design in order to be sure that you've the output when you wanna check it, it'll be better to add another state as I've done here down for you. I think that all your code is synchronous with a clock so all is under a clked process.
when state1 =>
sum <= ("000" & a) +...
Re: Why Gray and Johnson state encoding avoid metastable sta
The idea is that with that code only 1 bit change each time and so also you're sure that when one change the other still be the same and so you don't have problem about the 2 commutations.
Example
only 4 state = stateA, stateB...
shift register vhdl
Your way is fail.
In VHDL you don't need to use the loop!
That's the solution:
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shift_register is
port(
clk : in std_logic;
rst : in std_logic;
d : in std_logic_vector(7 downto 0)...
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