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Recent content by mishrashashi

  1. mishrashashi

    HFSS: S-parameter simulation of Connector

    Thank you all, for your kind reply. I know how to simulate the circuit and get the result with S-parameter model. Earlier I have received models for connector also. I have only step file. I know that HFSS can do S-parameter modeling. I'm just beginner in HFSS. I have to learn this tool but this...
  2. mishrashashi

    HFSS: S-parameter simulation of Connector

    I am working on client project and can't share any data here. Connector has 12 pins in two row. (Similar as berg strip) Please, let me know steps involved in S-parameter extraction for such type of connector module.
  3. mishrashashi

    HFSS: S-parameter simulation of Connector

    I have Step module of board to board connector. To simulate complete circuit, I need S-parameter of this connector. Please help me, how to generate S-parameter model from a STEP file.
  4. mishrashashi

    [SOLVED] HFSS: Two different materials intersecting error

    I am simulating one connector in HFSS. I have assigned different materials for pins (Copper alloy) and body (Polyester). While validating, I am getting error of intersection. How to remove or ignore this error? please help. I'm new in HFSS.
  5. mishrashashi

    I want know create library using data sheet

    Hi Follow these steps- 1. Create pad for ball grids of size defined in datasheet. (tool- cadence> Pad designer) 2. open Allegro editor. File>new -->package symbol> add package name 3. set the grid as per your requirement. 4. Add library path for pad and psm files. 5. go to Layout> choose pins...
  6. mishrashashi

    Diagram question - need help understanding

    I spent lot of time to solve this, but got puzzled in numbers. 149, two logic gates. then in second picture some formulas and numbers. Can you post the answer? If it is personal then, leave it. Hats off to this guy.
  7. mishrashashi

    How to manage "side" projects

    I can suggest you to use wiki redmine. it is user friendly. I have experience with this tool. it is helpful to me to manage several projects on single platform. you can create project wise pages. where you can track your work effort. if a team is involve in project, individuals work also can be...
  8. mishrashashi

    How to manage "side" projects

    There are several project/task management tools are available for free. you can check "redmine wiki" tool for your purpose. Also, you can manage your task on online tools like- Teamwork
  9. mishrashashi

    Geometry stitch failed warning in HFSS

    Hi all, I am doing HFSS simulation for combination of FR4 PCB and Metal PCB. My simulation failed after running several hours. There was a warning message-"Geometry Stitch Failed. Falling back to backup process". I'm using HFSS 15.0 (64 bit) for analysis. Can anyone give me idea what is this...
  10. mishrashashi

    Best software for Gerber viewing and printing

    Best Gerber viewer is GC-Prevue for Gerberber viewing and printing. Another good software is viewmate from pentalogix.
  11. mishrashashi

    PCB SI tutorial tutorial, guide

    Did you visited cadence portal. There are several white papers. Here is a white paper/userguide for DDR simulation
  12. mishrashashi

    To convert brd file to siw file

    Ansys Siwave imports two files to open any design. 1. Ansoft Neutral File V2 (*.ANF) 2. Siwave Component file (*.CMP) to export .BRD file to .ANF & .CMP files, you need to install ANSYS GUI (comes with Siwave) on the system on which cadence is installed. After installation you'll find Ansys...
  13. mishrashashi

    DDR2 Timing (interconnect) budget calculation

    can you share block diagram of DDR section of your design? Please mention how data and control signals are communicating.
  14. mishrashashi

    Can this be an impedance-controlled transmission line?

    There are two types of Differential Pairs – ODD mode and EVEN mode. ODD mode is more commonly used. - Signals have return path on adjacent layer. - Impedance of differential signal depends on: height of substrate, width and thickness of trace, spacing between traces. - Impedance also...
  15. mishrashashi

    DDR2 Timing (interconnect) budget calculation

    Hi Balamani, for DDR2 timing analysis, please follow datasheets(processor) timing diagram. you have to map timing delay between clock to DQS, then DQS to DQ. CLK to Address and Command. If you can share part name/ datasheet of processor. I can guide you in timing budget calculation. For...

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