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Recent content by microww

  1. M

    How to eliminate "assign" after DC synthesis?

    when you have tri_state bus or ports ,you will have "assign ";or when you have some unconnected pins ,you will have the "assign ". You can add boundary_optimization and set fix to remove the "assign"
  2. M

    How to specify the clock in the SE'gcf file?

    Thanks ! Now it works!Something is that we can not do some operation on clock but just use as clock trigger!
  3. M

    How to specify the clock in the SE'gcf file?

    oh my god! No one can help me ?! Today I fand some solutions for these problem,but I dont know whether it can work!Just try it!
  4. M

    aegean.chou can you help me?

    I have some problem about SE.Can you give me some advice? Now I just design a digital sysntem.When I proceed the P&R,I meet some problem: 1.I dont know how to specify the generated_clock in the core?If I use "Level 0 "to specify the clock ,I can't create the clock tree!How can I do ? my...
  5. M

    How to specify the clock in the SE'gcf file?

    Now I just design a digital sysntem.When I proceed the P&R,I meet some problem: 1.I dont know how to specify the generated_clock in the core?If I use "Level 0 "to specify the clock ,I can't create the clock tree!How can I do ? my clock specification is : " (GLOBALS_SUBSET TIMING...
  6. M

    which is the best tool for CLOCK TREE SYNTHESIS-(CTS)

    clock tree synthesis tool I always used SE to generated CTs Abd Apolo of synopsys also can do that!
  7. M

    Difference between FPGA and ASIC codes

    some question about ASIC Thank you! Now I also have same questions: 1.at ASIC, how to temp with the interior data bus,with MUX-selector or Three-state-bus? 2.,how to set accordingly variable of DC constraints to terminate the "assign" definition at the netlist after DC
  8. M

    a DC synthesis problem

    gtech_not May be you can specify the work library and symbol library again at .dc.synopsys.setup file! Or you can get help from synopsys command problem"man LINK-5"and "man DDrb-44"for detail information!
  9. M

    can verilog read binary(like .obj) files

    I uses $readmemb(),but I can not read into the memory when I pre-simulation at Modelsim 5.6,why? I have put the test bench and *.vec at the same path! Sometimes I can read into the memory,are the software-Modelsim had some problem?
  10. M

    Difference between FPGA and ASIC codes

    some question about ASIC 1 .Any one can tell me the differenences about code for FPGA and for ASIC? 2. How I can specify the I/O pads,after DC or at verilog code?
  11. M

    Open-drain resistance for a pad

    may be you can add pad after DC ,add I/O pad at netlist after you had compiled by hand directly!
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