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Recent content by microtronics7

  1. M

    Bias current for Opamp in bandgap

    Can anyone suggest me an opamp architecture where Vdd noise appears at the O/P. I am in need of such architecture....
  2. M

    Bias current for Opamp in bandgap

    But in most band gap design they use 2 stage miller opamp. What is the adv of folded cascode over two stage milleer?
  3. M

    Bias current for Opamp in bandgap

    But I want the rules to be followed for bias current selection during op amp design. Is 500nA a good option?
  4. M

    Bias current for Opamp in bandgap

    Hi, I am a novice analog designer. I am going to design an opamp for bandgap application in 130nm technology. My opamp should have High gain good bandwidth low offset low power. Maximum on current is 5uA for entire bandgap I have chosen two stage miller opamp. 1. How shall i choose my bias...
  5. M

    Cadence IC 610 installation

    Dear friends, I want to downloaded Cadence IC 610 through net and I want to install in windows 7. There is no .exe or setup file which can initiate installation. Thanks!
  6. M

    Design rules for custom VPX boards

    Hello Teachers, I am a novice in boards and backplanes. I have the following doubts: 1. Is there any design rule for custom VPX boards? I mean is there any predefined pins for power , gorund etc. 2. Is it entirely upto the designer to plan and route everything and then simulate for the...
  7. M

    Dynamic power dissipation using X power in xilinx ise

    Dear Sir, I am simulating a multiplier in xilinx ise. i want to find dynamic power and plot it against time and frequency using xpower. But it shows 0 dynamic power. I used a clock to feed the inputs and generated a vcd file by the following codes in test bench; $dumpfile("vcdfile.VCD")...
  8. M

    problem generating vcd file in xilinx ise

    Dear amraldo, I replaced with 1 but it does not make any difference. Is there any other way i can find dynamic dissipation of my multiplier. I have made it power efficient by reducing switchings. I am using xilinx ise. Simply using xpower shows dynamic power to be 0.
  9. M

    problem generating vcd file in xilinx ise

    Dear Sirs, I am trying to find out dynamic power consumed by my multiplier. So i want to generate a vcd file. I am using the following codes in my verilog test fixture initial begin $dumpfile("invchn26.vcd"); // Change filename as appropriate. $dumpvars(0, generator); $dumpall; $dumpflush...
  10. M

    How to use Xilinx ISE schematics in Cadence?

    Dear Sir, I am simulating a multiplier in xilinx ise. I have written structural verilog code . Now i want to transfer the schematic to cadence. May I transfer it directly? I dont want to build schematic in cadence from scrap. Pls explain in detail since i am a novice. Secondly, i want to...
  11. M

    recording adc output for inl dnl

    Hello teachers I m designing a flash adc in cadence. I have completed the schematic only. After applying ramp how can i record the digital values from the ROM lines . I want to find which code appeared and record large samples to find inl dnl. i want to find inl/ dnl using histogram method...
  12. M

    How to measure the parameter of ADC, such as DNL,INL and SNR

    Re: How to measure the parameter of ADC, such as DNL,INL and I am designing a 6 bit flash adc in cadence. How can i evaluate inl and dnl. I think i have to write the digital output to a file. How to do that? Can matlab be used to evaluate inl dnl by importing the above file.
  13. M

    adc simulation in cadence

    I want to find inl dnl of my 6 bit adc. Pls tell from initial level i.e. from basic. I have completed the schematic only. I think i need to connect a ramp input. Then to what should i connect the digital output of my binary ROM. How can i store the digital outputs i.e. samples.I am using a...
  14. M

    adc simulation in cadence

    Hi I am a newbie. Can anyone help me in doing basic adc simulation in cadence
  15. M

    inl dnl of 6 bit flash adc

    adc inl/dnl Hi! I m a beginner and trying to simulate a 6 bit flash adc for its inl anf dnl in Cadence. Pls help me to do it in cadence.

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