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Hi praveenlb,
Here is an example of complexity - it has "Enough multicolored LEDs to function as a disco ball"
https://www.dinigroup.com/product/data/DN2076k10/images/front.jpg
How to design? Start with this book:
**broken link removed** by Kraig Mitzner
Hope that helps,
Cheers
Hi buenos,
How about this way ?
The XAPP 859 should be fine for the first try, it moves a data from DDR2 mem space, into the system memory space (PC). You could put a mux in-between the PCIe engine and DDR2 memo controller, which allows you to load the DDR2 with the ADC data, and then move...
Hi buenos,
Short answer about coregen design (PIO): NO, you still need to do some work to interface to PCIe block to your wishbone. Everything depends on your motivation - it's not a rocket science :D
Have you tried to dig into the code/doc of the XAPP 1052, XAPP 859, and S6 connectivity kit ...
Re: Short-Time FFT
Dear ravics,
Two approaches comes to mind:
1) CPU solution: instantiate a MicroBlaze CPU inside your Xilinx FPGA, and find (google) some open source implementation of the STFT (written in C). Then compile it for Microblaze.
2) Non CPU solution, You probably would need a FFT...
Re: FFT implemented using FPGA
To add some reference.
Please see this paper: http://www.andraka.com/files/HPEC2006.pdf
You can find there a really good description of the FFT in the FPGA. After reading it you should get some general knowledge about FFT algorithms which are best suited for FPGA...
Hi jason_tian,
Did you check if Quartus II 5.1 supports the $readmemb system task?
Start Quartus and open Help. Then search for "System Tasks and Functions Verilog". You can check if the 5.1 supports $readmemb.
This is a example which uses $readmemh and in Quartus II 6.1 it definitively...
Re: FFT implemented using FPGA
Hi yongqin2005,
The best source about how to implement FFT in the FPGA is comp.arch.fpga newsgroup. You will not find source code for FFT over there but lots of good advices about implementation.
You could try also the "Digital Signal Processing with Field...
Hi,
This should be a good starting point:
https://www.altera.com/end-markets/refdesigns/sys-sol/computing/ref-sdr-sram.html
Documentation and source code ( Verilog/VHDL ) included.
Good luck,
mhmhmh
If you have some experience with uC then go with NIOS. When you are done with "Neural Network in C" come back here. It should take you no more than one week.
Search Altera's website for the tutorials and user manuals.
If you don't have experience with VHDL read this "RTL Hardware Design Using...
The M4K is just a dual-port (DP) memory available in the EP2C20 device.
I haven't though to much about your application but I see that you could use DP mem to store your coefficients. Then you can use first port to read them out, and the second one to update them (coefficients).
If you have to...
Hi pranavam,
It looks like you need a memory for coefficients which can be updated from the FPGA firmware. The M4K can fit your needs. Please google for the "FPGA neural networks" and "FPGA adaptive filter". This could be useful https://www.us.design-reuse.com/articles/article5868.html
There...
Hi pranavam,
Unfortunately the newest Altera chips do not support PR/DPR, neither the Quartus. But if you want to play with PR the better way is to go with Xilinx.
Apart from the PR/DPR support in the devices you need a software for the PR. At the moment the most advanced PR support is...
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