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For some reason I have to adopt the structure below to provide the ESD path from vdd to vss.however, I don't know how to choose the value for R and C. If the size of the NMOS changes, how does it influence the ESD ability?
Two branch is better only if the structure doesn't bring any other mismatch.
Matching of 1:100 is more difficult and also cost more layout area because of the process ununity.
The first step you have to design a voltage reference with usual performance.
The next step you could improve the performance and consider the nonlinear factor.
You should refer to analog CMOS design of Razavi and Sansen.
Re: maxsideband in PNOISE analysis --> it doesn't be conv
read spectreRF manual first.
"I think that the maxsideband and number of harmonics have same value, doesn't it? "
it doesn't.
Hi,see the attachment it's a fully differential opamp ac character testbench.
The opamp work at an open loop state.
1GF input decoupling capacitor transmit ac signal to each input but prevent the dc signal.
1GH inductor help set up the input operating voltage but prevent the ac signal
Add ac...
There is some problem when you build your tree structure.
Have you included the verilog netlist file in your top level netlist?
Check your netlist structure to see how your port between analog and digital are connected together.
To do that First you create a cellview with veriloga-editor in the spectre,for example named "vco",and then "vco" will appear in the cell and "veriloga" will appear in the "view" box.
It's a text file you can edit with noise table function. When you exit the file the system will compile it . If...
The syntax of noise table you could refer to this article.
https://www.designers-guide.org/Analysis/PLLnoise.pdf
There is an example at page 22
Good Luck!
construct a test bench which is closed loop and gain=1.add a vdc =0 as the input of the opamp.
Spectre provide noise analysis. you could choose the differential output as the output pair. and input source as the noise source.
After simulation you could print noise summary to see the total noise...
modeling PWM stage
Hi,I am modeling a PWM stage.
it's usually modelled as a linear gain stage whose gain is VDD/VTRI. VDD is the power supply voltage,VTRI is the swing of the carrier.
My question is: this linearization model doesn't consider the phase factor. sometimes there is a large delay...
do you mean the bw of the integrator?
I think if you design the bw to 20k, in the audio frequency range you can't obtain a uniform phase shift.
however,if you want to get a better THD,you should enlarge the bw.
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