Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
hii..
i am going to do a project on built-in self-repair.In this project am going to design different size of RAMs (8kB,16kB,32kB)etc. and those rams has to be tested using bist and then they has to be repaired.So pleas help me by giving an example like how to design a 8X8 RAM with 8rows and 8...
hi all....
i am doing a project on built in self repair for rams.Can u please suggest me which algorithm i have to use for it and why that only?
if it is walking 1/0 test how it is different from others and why we choose it?
please give response as soon as possible..
thanqqqqq
hi..all
iam doing a project to test the rams using bist and repairing them using BISR.
please iam requesting you to suggest me which algorithm is used for BIST for testing rams?
how to design random access memories using verilog or vhdl? and what is the tool we have to use for it? is it possible with model sim?
please respond to my answer as soon as possible.
thank you..
hi.....
iam doing mtech.,and i did my mini project on design of two stage op amp...
now i am interested to do a major project on analog only...please suggest which project will be good for me to select...
How to design a two stage opamp with the following specifications?
1.Gain =1000
2.Input reffered offset = 5 to 10µv
3.Phase margin=above 60dB
give me the complete design process
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.