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to correct a concept, cascode a switch to turn on/off a current mirror won't cost any voltage head room, if the device is big enough, the VDS drop across it shall be at a few mV, so totally not a problem, you can simulate it out and verify my words.
we use this kind of connection everywhere...
option 1:
as you said, to modulate the bias current of your source follower, but I suggest the best way is to design a source follower at 300ohm, and duplicate 6 of them in parelle to match well. then you can choose to turn on 4 of them to achieve 75ohm or 6 of them to achieve 50ohm.
option 2...
pay attention to the current loading of your regulator, sometimes, if current loading is not stable during power up, say, too small current, then the output voltage may fluctuate heavily, if your regulator is the traditional sample and feedback type.
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and to continue on...
65 nm drc rules
wow, you are asking about DRC rules of layout, which is usually classified spec for a fab line, and not easy to get. Different fab may have slightly different rules for layouting, which is dependent on their process technology.
in voltage buffer design, people usually cares about output voltage swing and ignores input swing, for example, a normal OP with N type diff pair biased and an current mirror device, connected like a voltage buffer, it can only work at the voltage bigger than Vtn+200mV+Idsat_mirror, use the same...
Dummy generation
I guess zoraide's question is how to generate those dummy metals, the DRC run set tool only checks them. till now, we don't have an existing tool to do this, so we developed a script to finish this job, but unfornately, the script will lead to a lot of DRC errors which need...
falsh locking happens when the delay line is too long or too short, where it goes 1 or more cycles ahead, and still can reach the lock status. don't know how to fix, might need very careful control at the beginning of locking operation, use a counter or something to limit your delayline range.
define clamping in cmos
in our process, we stacked two mos transistors which can tolerate 2V operation range to be a 4V tolerate clamp, which is similar to your problem, in this clamp, the discharge path is through two serial connected mos transistor. and with an extra RC timer to control...
Role of Test Chips
Test chips usually goes before real product to collect the following data:
1. Characterization of key devices, for choosing the right circuit structure.
2. failure density, for redundancy and architecture design reference.
3. to test new ideas of circuit implementation for...
breakdown voltage 65nm
and to add on to ESDSolutions' comments, whether the MOS cap is at risk of ESD stress is also heavily relying on your ESD protection scheme and quality. usually high ESD current should have designated path, around the IOs, and all internal voltage rise shoudl be...
n-mos device placed in deep n-well is called tripple well N-device, best usage is to pass negative voltages efficiently or overcome the body effect as a current-passing device.. as for the Vt or other performance parameter, it all depend on processing, may or may not be depletion type. in our...
and you can easily use verilog-A to build define an analog circuit block like controllable delay line, filter and stuff, and use it in your system level simulation without even having the circuit. so that you can quickly evaluate your system performance and define specs for each components.
20k resistance by poly, will be a big area cost, if not so strict, n-well resistor is also a good choice. and 100pf capacitance can easily be done by mos gate cap (grounding drain and source).
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