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Re: Are there a lot of job opportunities in electronics in U
it's hard to compete with local ppl in ASP.
In china and India, students work very hard and are well trained in EECS, besides they are much cheaper then hiring a foreign engineer.
Just installed a new PDK for Cadence.
When I do DRC for layout, it keeps showing error like
# INFO I/O PADS = WIREBOND#
Could anyone give me some suggestion on how to fix this problem?
I'm not a CAD guy:(
cadence vco oscillation tricks
i just simulate a very basic LC cross-coupled VCO in Cadence.
trans analysis.
It's weird to me that the results is subjective to simulation time.
say when simulate 20ns, I can see the oscillation wave, while if i change to 10ns or 30ns, the wave is gone and...
Re: offset cancellation
also, how does the floating gate tech. help in this case?
floating gate in analog means u can adjust the charge stored on it therefore the Vth. normally for low-power application.
do u mean this can help to improve the Vth matching?
for cap feedback, do u mean...
wanna earn lots of money? then u must find the killer application.
as analog IC related,
either consumer electronics : say build-in DC/DV(high quality comparable to cannon products ) cell phone . mini-cinema in car.
Or biomedical micro-chip, say implanted into human body to dynamically...
hi Colbhaidh
once again, i'm confused.
As power consumption in analog IC is mainly due to DC biasing (and the biasing current is always there), why bother the leakage?
It’s true, that makes the transistor a bad switch, and will cause signal leakage, CFT etc. But those r performance issue, not...
biomedical signal is analog in nature, and if u wanna process it through the powerful digital machine, u need a mixed signal interface anyway.
whther EE designer play a big role in that industry? who care.
coz it's always the boss who play the big role.
As a emplyee, u r slave no mater EE or...
Re: offset cancellation
yes, offset is a problem.
but talking about the gain stage, generally the gain comes from the ratio of capacitor in a SC circuits, and i don't think the offset will be amplified in that way.
and normaly, the offset of a opamp is a constant value, thus not hard to...
90nm hspice library
i have the same question.
com pushed for 90nm design.
anybody have 90nm analog exp?
to resolve biasing issue, no coscade sturcture allowed, not mention gain boost tech.
does that mean it becomes very simply signal stage amp? similar to those used for RF? then how to...
Colbhaidh's post is really informative. i appreciate that.
my question:
AS to so called "advanced nosie cancellation techniques", seems to me most of them r just duplicate ur circuits more and more and then applied a inverse CK(or any noise source), is the overhead a little bit high?
could u...
Re: mixed signal IC?
i'm working on mixed-signal SoC.
Challenges actually lay on fab. but not design.
An Intel manager have claimed that SoC is dead meat for the high cost, while TI try all they can to fight back.
For multi-thresholds:
It is basically a power issue. As I said power consumption in analog IC is mainly due to DC biasing current, means no tricks on switching factor. Multi-threshold is desirable since when u scaling VDD, u can still have decent signal swing by scaling Vth, besides the leakage...
how to become an analog ic design
Seems to me that quite a few ppl on this board r doing analog IC design or relative stuff.
Let us share and discuss some idea and prospective in the area.
1. Shrinking feature size.
Digital has come to 90nm, while analog doesn’t scale that fast and has a...
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