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Dear all,
Can someone tell me why the current through an inductor rises linearly when a constant voltage is applied across an inductor. Please don't explain in terms of equations because I know V = L * dI/dt and so I is the integral of voltage applied over time and therefore I = ( V * t ) /...
Dear All,
I would be really happy if someone could explain how the circuit: 5A Constant Voltage/Constant Current Regulator given in the LM317 datasheet works. I have built this circuit and it works like a charm. Really good circuit for experiment purposes.
Circuit:
What are the...
HI,
Regarding your first question:
Please go to 4017 datasheet and find the rest pin for the IC. Connect the fourth channel to the reset pin so that when the fourth channel becomes active, it resets the count and the first channel becomes active.
Second question: Please...
Hi all,
I'm planning to buy a DSO, mostly for my hobby purposes(private use) and I would be using it for FPGA and microcontroller based projects. I have been doing some market analysis and came to a point where I should choose between two models:
1) TDS-2012C from Tektronix --
100MHz, 2...
Hi kalyansrinivas,
If you want to do it using software, do as follows:
Wait for input A to become high and once A becomes high start a timer. If input B is already high, wait until it goes low and when it again goes high, stop the timer. The timer value will give the phase difference.
If...
Hi everyone,
(all references to an N channel JFET)
The book: 'Solid State Electronics Devices' by Ben G. Streetman says that the depletion regions on both sides in a JFET MEET near the drain as the drain voltage is increased which essentially pinch off the channel(with gate voltage = 0).After...
Hi Naumanpak,
From the datasheet:
"The RCREG is a double-buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection...
Hi TsAmE,
Yes, but it happens only in an ideal capacitor after infinite time.The capacitor charges near to the applied voltage after few time constants (time constant = R*C ) , say six. You may put t=6RC in the equation I mentioned and you can find that Vcap=8.977V.
Hi quietfoot,
You have to use 4 JK flip-flops, with asynchronous set and clear. Wire the JK FFs as T FFs by connecting J & K pins to a logic high. Connect the Q output of first FF to the CLOCK input of next FF and so on.
Next you need a combinational logic which upon detecting a '1010'...
Hi TsAmE,
When the capacitor is fully charged, ie, when it is at 9V, there won't be any current flow (provided, the capacitor is loseless). So there won't be a pot difference across the resistor.
Hi TsAmE,
No, the asymptote would be at 9V. Let the capacitor charge to 9V which happens at t = infinity. Now what the resistor sees is 9V on both its terminals. So there won't be any current through the resistor which means no drop across it.
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