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Recent content by mansi0905

  1. M

    need help with tanner eda licensing error LSERVRC not found

    i am tryng to use tanner eda licensed version where the license is provided via dongle. the problem is whenever i try to open sedit after pulging in the dongle it shows following message. i would like to mention here that i have already saved the .tlu files in the utility folder. the message...
  2. M

    LLC resonan converter small signal modelling

    can anyone help me with small signal modelling of LLC converters. Please tell about the procedure of small signal of LLc converters in detail. Thanx In advance
  3. M

    how to perform division by three in xilinx

    the operation is being performed in integer so i guess 32 bits. how can i use look-up table in ROM for division pls elaborate
  4. M

    how to perform division by three in xilinx

    i need to perform division in vhdl in ise environment by other than powers of two. i need to do this in single clock cycle. i facing this problem since ise environment does not support division by other than powers of 2 pls help thanx in advance
  5. M

    pid controller vhdl code

    sorry i am not getting what should be done . could you please explain a bit more about the suggestion
  6. M

    pid controller vhdl code

    i tried this code but simulation results show u_out as undefined for all the clock cycles. thanks a lot for help
  7. M

    Should there always be a rest??

    yes there should always be a reset . it prevents the signals from getting undefined values or garbage values especially when you do hardware implementation
  8. M

    pid controller vhdl code

    here is the new code for pid library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if...
  9. M

    pid controller vhdl code

    thanks a lot for d suggestion . i have replaced e_prev2 e_prev1 . yes it was an error but then also it was still giving same result . then i tried using variable inside process then the output of pid was undefined for all the clock cycles. pls help
  10. M

    pid controller vhdl code

    i have already checked the code . i don't think dat there is prblm of multiple drivers. here is d code. pls lemme know the error in dis vhdl code . entity pid is port( u_out:out std_logic_vector( 15 downto 0); e_in:in std_logic_vector(15 downto 0); clk:in std_logic; reset:in std_logic); end...
  11. M

    pid controller vhdl code

    i have to design a pid controller for controlling the duty cycle. the problem is wrote a vhdl code but they simulation results show undefind output of pid evry alternate clock cycle. i am not able to underdstand the problem. pls help.
  12. M

    Help me find the error in this code for generating clock pulse at lower frequency

    hi ! can anyone help i could not find the error in this code. i need to generate clock pulse at lower frequency . entity clkgen is Port ( clk: in STD_LOGIC; clk1: out std_logic; c1: out std_logic_vector( 5 downto 0); reset:in std_logic); end clkgen; architecture Behavioral of clkgen...
  13. M

    adc and dac of spartan 3an

    can anyone provide the source code for spartan 3an adc and dac interface . ineed to study it , moreover i have the source code for 3e .will it work for 3an ? pls help its urgent . thanks in advance .
  14. M

    i need vhdl code for 32 bit fft processor

    Re: vhdl code thanks for the help but i need coding in vhdl not in verilog for 32 bit fft processor.
  15. M

    i need vhdl code for 32 bit fft processor

    Re: vhdl code its not there on embedded tips blog spot . kindly help . i am not a members of opencores.org
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