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Recent content by manojkhandelwal

  1. M

    how to find number of clb utilised in spartan3

    Hi, Can u please tell which tool you are using for your design? There is no such thing as formulae. The tools will calculate and give you the area and timing of your design. Thanks, Manoj
  2. M

    IN industry prefer VHDL or verilog?

    Hi, If you know any one that is enough, the interviewer always asks which one you know (atleast it was true in my case). Thanks, Manoj
  3. M

    a problem about a^2 in VHDL

    Hi, yeah! you are right ....but multiplication of higher widths (a*a) will also have larger delays (multiplier delays also depend on the widths as far as i know). But again iam not sure .........may be multiplication is the only best way, because all FPGA tools will synthesize it into a...
  4. M

    a problem about a^2 in VHDL

    hi, sorry i messed it up!!! look at this now 1 + 0 =1 2 + (0+2) = 4 3 + (0+2+4) = 9 4 + (0+2+4+6) = 16 5 + (0+2+4+6+8) = 25 6 + (0+2+4+6+8+10) = 36 7 + (0+2+4+6+8+10+12) = 49 now its perfectly fine!!! Thanks, Manoj
  5. M

    a problem about a^2 in VHDL

    Hi, Here is a way which i saw somewhere 00001 + 0 = 00010 (2) 00010 + 2 (0+2) = 00100 (4) 00010 + 6 (2+4) = 01001 (9) 00100 + 12 (4+8) = 10000 (16) 00101 + 20 (8+16) = 11001 (25) ........... Iam not saying that this can be efficiently be implemented in digital...
  6. M

    8 bit to 96 bit conversion

    Hi, Now the question seems to be clear... You need to have registers and a counter which will count the number of clock cycles for which input data should be buffered...(in your case 12) also you can implement small control logic around the registers which can signal buffer full, empty etc...
  7. M

    How to find gate counts?

    Well i think you can get a good rough estimate from the report.by knowing how many registers are used and as how the LUTs are configured...if in case you just want to compare the gate counts of your vhdl codes But, if you really want the exacy gate count, and your design is large i dont thing...
  8. M

    include problem...please help

    Hi, in the test bench you did not include the file which contains your top module "count" ... you have included "icnd.v" which is not your top module, and doesent contain module "count" It should give error for module instantiation itself.... Thanks, Manoj
  9. M

    How to find gate counts?

    Hi, ".mrp" file contains the details of resource utilization of your device...it will be in your implementation directory you specified Thanks Manoj
  10. M

    include problem...please help

    Hi, post your icnd.v also Thanks Manoj
  11. M

    include problem...please help

    Hi, its really confusing what is your icnd.v ? is it the one which has module count or module icnd? may be i can help if u give clear info... Thanks, Manoj
  12. M

    Verilog Coding Problem

    You must write 'include "filename.v" in your file where you have your top module or where you want to use that module Remember 1. It should be filename.v and not modulename.v 2. make sure that file is in your current directory (better do it this way).......otherwise you need to specify...
  13. M

    Verilog Coding Problem

    Hi, 1. If u wnat to have two instances of a module, it doesent mean u have to define the module twice (shift8 and shift_load). 2. Have a top module where you instantiate all the modules. You are doing it in the testbench. 3. In the testbench try to instantiate only the top module. 4. Also you...
  14. M

    [SOLVED] using all conditions in if else statement

    Hi, reg is the only legal type on the left-hand side of an always block,and hence address should be of type reg Please make this point clear in your mind "Just making (address) or for that matter any net of type reg DOESENT mean that it will infer a register" Also,avoid inferring latches...
  15. M

    Verilog Weird Error with logical correct code but has errors in compilation

    Hi, Put assign in front of all your assignment statements... Combinational logic is implemented in verilog using either assign statement or always block. Also, your code is redundant...(assign O = M ^ Y is enough) What is the use of Verilog then? Thanks, Manoj
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