Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by madhavisai

  1. M

    ET(encounter test architect) tool help

    I am not getting any errors in flows of methodology adviser but i cannot able to see output in schematic window.I am getting only toplevel view.......if i go forward trace circuits which always showig x/x logic on all the pins
  2. M

    What events are not synthesizable in Verilog?

    events in verilog A changa on input is treated as event in verilog
  3. M

    ET(encounter test architect) tool help

    Hi santhosh I did all the steps given by u before only... But my problem is that i can't able to see output on schematic window all pins are showing x/x logic. Thanks for sending ET doc. bye madhavi
  4. M

    ET(encounter test architect) tool help

    I can't get exact details plz help me santhosh007
  5. M

    Q about Encounter Test - different from SoC Encounter ?

    Q about Encounter Test hi Encounter test architect is totally different fron SOC .this tool is used for testing a design and in this tool we hae Built in RTL compiler if ia am right
  6. M

    ET(encounter test architect) tool help

    encounter test architect tutorial hi everybody I am final year M.tech student ...and doing project in dft tool like ET from cadence we have license for this tool but i am new to it Can anybody help me how to work with this tool Thanks in advance
  7. M

    i want Encounter Test tool reference

    Thanku very much thanku
  8. M

    About dft FAULT COVERAGE

    hey u doing work on which tool actually i require help for Cadence Encounter Test architect tool can u give the required material plzzzzzzzzzzzzz
  9. M

    Why is the $monitor system task in Verilog defined inside an initial statement?

    verilog $monitor Since this system task continuously monitors the values, it needs to be invoked only once and hence, it is typically invoked in the initial block since the initial block is also invoked only once during the length of the simulation. However, it is not necessary that the...
  10. M

    I am a Student, How can I get my chip fabricated

    students projects will be fabricated with free of cost if u send the gdsII to the foundary
  11. M

    Which one is preferred in FSM design ? Mealy or Moore? Why?

    mealy or moore always moore fsm s are stable go for moore
  12. M

    $monitor system task in verilog

    verilog monitor statement It is used to view outputs in text format on console
  13. M

    Need info about "moving message display implemented in FPGA kit in VHDL"

    About project help first u need to use a counter to down the frequency fron FPGA to 1hz.after that use a counter to generate the sequences like alphabets in our lab we did for "CVR CE VLSI" so we have given counter output 1 as C,2 as V like that we have coded.and then use one shift register...
  14. M

    question reg RTL coding

    In RTL we assume that the code we r writing which is a vector quantity which will transfer betweenfunctional units.
  15. M

    i want Encounter Test tool reference

    This is not soc encounter its is encounter test architect tool which is specially meant for testing
See more

Part and Inventory Search

Back
Top