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Recent content by MAAASD

  1. M

    FPGA advantage 7.2 on win7?

    This works for me! Thank you very much :)
  2. M

    Changing the back ground in cadence IC5141!! please help

    This video will help you https://www.youtube.com/watch?v=JivgqYabhWI&list=PLYWwUnNUBdpSzQK0yANKPgmzRKttTgZY9&index=13
  3. M

    Global Nets Cadence-Virtuoso

    Hi guys, I hope all is fine. I have seemingly a simple question, for the schematic below i want to connect the voltage source nets to all the input pins of the compenet; i know that one solution is to add wires to these pins and name them same names as the power nets but for a large design...
  4. M

    How to find shcematic view of every standard cell in my digital library

    Hello all, In my digital design kit, there are many folders gds lef symbol synopsys verilog and so no ,,, what i want to do now is that, i want to import the schematic of every standard cell into virtuoso. the problem is that, i did not find the folder called "Schematic" or "virtuoso" in...
  5. M

    DPLL (Digital Phase Locked Loops )

    Please, can anyone help me ?
  6. M

    Digital design projects

    yes sure i've already read this book, actually it was great book! now i want to know other books to read :) Thank you very much!
  7. M

    Digital design projects

    Hi everybody, I need a good reference book to help me making good projects and examples in digital design and computer architecture i love these fields and already have the concepts of them and i've learned the verilog hdl and the next step for me is to make some projects and examples in...
  8. M

    DPLL (Digital Phase Locked Loops )

    Hello all, I'm preparing for my graduation project which is (a Verilog implementation of the all digital phase locked loop ) and asking if you can recommend me any good books or references about this topic, and any tutorials on how to make the chip layout on cadence and calibre . (i really...
  9. M

    [SOLVED] PicoBlaze ROM Problem

    @ads-ee I started new project and used the same file and the error had gone, although i did not edit anything ! but thank you very much for your time :)
  10. M

    [SOLVED] PicoBlaze ROM Problem

    Hello Friends, In PicoBlaze softcore microcontroller of Xilinx i've got the HDL file of the instruction ROM and i've made the top level HDL file which combines both the PicoBlaze softcore uC and the instruction ROM but when synthesizing in xilinx web pack , this error appears...
  11. M

    What's your best books on FPGA prototyping and projects using verilog HDL?

    I'm interested in the filed of digital design and i prefer using the verilog HDL so can you help me to find projects can be implemented using verilog ? i've bought the spartan 3E kit board and willing to do nice projects on it . What's your best books on FPGA prototyping and projects using...
  12. M

    spartan 3e starter kit problem! HELP!

    i've tried it and it works like a charm! Thanks a million.
  13. M

    [SOLVED] Spartan 3E Starter Kit Board - PROM Problem

    Finally i've found the solution to this problem! on this topic https://www.edaboard.com/threads/104093/ check this post i've tried it and it works like a charm! Thanks a million.
  14. M

    [SOLVED] Spartan 3E Starter Kit Board - PROM Problem

    i've tried another file and same problem occurs

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