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Recent content by luoyanghero

  1. L

    low power design with UPF & DC

    Yes, PrimeTime is a good tool to calculate power. But if we do not have the specified library(eg: need t28nm, but only have s40nm), PT cannot calculate the accurate power value.
  2. L

    low power design with UPF & DC

    For RTL syn level, we want to know power distribution and power optimization space in RTL design. Does not need to the accurate power value. Can use a tool(like spyglass or VC_spyglass, not UPF) to get the power distribution?
  3. L

    What distribution is good for verification seeds?

    The richer verification seeds, the wider random configs, and the more fully verified. For example, the seed range is 1--10000, and 1000 seeds are generated. What distribution is good for the 1000 seeds?
  4. L

    How does parameterized IP verify completely?

    An IP has several parameters, and various parameter values can be combined in hundreds. As far as I know, coverage cannot merge parameters. What methods can be used to ensure that the validation is sufficient (all parameter values have been verified)?
  5. L

    How to save these verdi configurations as ordinary user?

    Use environment variables can solve this. setenv NOVAS_RC ~/novas.rc setenv NOVAS_GUICONF ~/novas.conf
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    How to save these verdi configurations as ordinary user?

    Verdi is installed on the server. I am an ordinary user and only have the right to use it. I made some personalized settings on the verdi GUI(such as changing the default editor to vim), but after closing verdi and restarting, these settings disappeared. How to save these verdi configurations...
  7. L

    Verilog use $random, why random seed be force changed? How use $random with seed?

    Thanks a lot. The following site given the $random details. http://www.testbench.in/TB_15_SYSTEM_FUNCTION_RANDOM_A_MYTH.html Seed is an in-out, so I need seed variable. ############## Random number system function has a argument called seed. The seed parameter controls the numbers that $random...
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    Verilog use $random, why random seed be force changed? How use $random with seed?

    //This is the verilog standard document discription: //The seed argument controls the numbers that $random returns so that different seeds generate different random streams. The seed argument shall be an integral variable. The seed value should be assigned to this variable prior to calling...
  9. L

    VCS2016 cannot compile ok

    My OS env is CentOS7.5; vcs version is L-2016.06; gcc version is "gcc version 4.8.5 20150623 (Red Hat 4.8.5-28) (GCC) " I use a synopsys lab for vcs env test. First run, it show me need add env 'setenv VCS_ARCH_OVERRIDE linux ' Then I added and try rerun. It should show me 'Simv generation...
  10. L

    How to estimate power consumption at the IP design level?

    Thanks a lot. gates toggle can be as a quantity for power coarse calculate. - - - Updated - - - 'W' is an absolutely unit. I want to find a relative unit.
  11. L

    How to estimate power consumption at the IP design level?

    description: In the IP design stage, sometimes there is no actual foundry-library to test IP performance, so will use similar foundry-library (or even any foundry-library) for testing. IP test points are: highest frequency, area, power consumption. As for area, we can use '2-input-NAND' as the...
  12. L

    Finding an IP Power Analysis Tool

    Rtl, waveform file, and foundry library file are required to analyze power consumption with spyglass. For IP designers, rtl and waveform files are available, but foundry library may not be available, which is not convenient for analysis. Is there a tool that only needs rtl and waveform files to...
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    Finding an IP Power Analysis Tool

    After designing an IP, you need to estimate the area, maximum frequency, and power consumption. As for the IP design level: the area can be estimated using the nand numbers; the highest frequency, given the process library, run the estimation using design compiler tool. But for power...

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