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Dear all i am using FPGA Spartan 3an (xc3s50an ) for some automation purpose ,i am new to this technology also i knew that this chip has internal EEPROM (IN SYSTEM FLASH MEMORY ) for non volatile memory storage of data . but i dont know how to access the flash memory address to store data and...
Re: xilinx dcm vhdl
hi in synthesis and simulation part this no issues but while implement in to the spartan 3an FPGA it provides only CLK50 output .......
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i changed the codings like this........
`timescale 1ns / 1ps
module DCM_CLOCK...
Mr ads-ee
Its really no words have with me to say thanks to you for your reply with very patience. can u send any web link for XILINX 12.3 ISE design suite step by step implementation procedure wit spartan 3AN ? Bec in CPLD only yet we are using for research so its little bit...
Mr ads-ee
Maximum how much external memory bytes can we add with xc3s50an ? is it possible to commuicate with i2c prorocol like EEPROM master and slave ? thank you.....
Mr.ads-ee thanks for your response but there is small change in flash memory .Its 64K not a 4K .
TECHNICAL SPECIFICATIONS
64K Flash Memory
16K RAM
UART-1number
Timer 16Bit- 2numbers
External Interrupts-3Numbers
Internal Core Frequency -100 Mhz
Minimum I/O - 60 above Pins
Package...
Dear all,
Presently we are doing some automation operation using micro controllers but i wish to change the technology to CPLD/FPGA .So, i wrote some verilog program in XILINX (XC9572XL) but it has 2 micro-cells of memory so i could not able implement the all coding in to that device ...
Can any one say is it possible to implement this code in ATMEL 24C16 EEPROM device for write the data.while i am implementing this with CPLD xc9572 I/O Pin declared as sda,scl there wont have write operation its operting frequency is 132kHz .voltage compatibility in CPLD is 3.3volt and EEPROM...
Dear friends ,
I want to store some data in to the CPLD -XC9572 Series device as non volatile information for the purpose of read that data when i need to receive that bits .Bec in my knowledge CPLD is the EPROM Technology basis ,So any one can clarify this doubt...
When i floor plan the constraints for CPLD device ,i am getting this error ,can anyone tell me the remedy for this .thanking you
Compiling vhdl file "G:/lokeshwarn/jc2_sch/jc2_top.vhd" in Library work.
Entity <FDC_MXILINX_jc2_top> compiled.
Entity <FDC_MXILINX_jc2_top> (Architecture...
While i am implementing the below verilog codings in CPLD -XC9572XL device the following error has been occurred .can anyone suggest me wat can we do for implement the same kind of various processes module codings (like phase locked loop,timer,automation purpose module) in single CPLD device...
thankkkkkkkkkkkkk youuuuuuuuuuu very much for your replay ..............
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hi...! but in xc9572xl device data sheet they have given that we can run the core frequency up to 120 Mhz .
but, external maximum crystal frequency is 40 MHz. So ,how should I achieve 120 MHz core...
Dears,
i have external clock frequancy of 40 Mhz in xc9572xl CPLD device ,i am very new for Verilog can anyone answer me for phase lock loop for obtain Fcco (output core clock frequency ) 120 MHz .how can i write coding for that?
thank you very much for all visitors and replys
hi i want to toggle the output led with one click of trigger input only at rising edge of the trigger input .after the trigger input the led will not stop to glow rather it must toggle from on to off continuously .can anyone suggest me the verilog code for this process.i am using this for xc9572...
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