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modelsim textio write
pls search ee.ant file.
where can you get the file?
i remember there will not be such .ant file after compiling the design.
puzzle me!1
ise edif verilog
in fact, i do not use XST. i just use Precision RTL or Synplify. those SW have the outfile what you want. i am not sure whether XST has this function.
and XST is one rtl synthesizer, so area constraints is no use for it.
it processes your design on logic level.
in edif file ...
Re: fpgaadvantage
maybe the coding style is not suitable for FA to convert to FSM.
if you have no hierarchy in you design, FA can not convert your design to block diagram.
meanwhile you should select the option of converting to FSA and block diagram when importing your verilog code.
hexfile xilinx
with the coregen window, you can use the memory editor.
you can import you mif file and then write to or save as hex file.
i think this can help you.
if it can not do this, you must retry to input the initial value of your memroy in the memory editor. and then save as hex...
verilog netlist to edif
yes. you can get it.
after you synthesize your design, you can select the output file which can be edif or verilog or vhdl.
when or after place and routing, you can not get it.
you can get want you want in this way.
good luck.
in fact i can understand what you mean .
which library do you want to use in ISE?
if you want to use coregen in FA, you can invoke the link in the task of hdl designer. but if you use ise7.1 and hdl designer is not the latest, you can not invoke coregen directly in FA..
in fact when you invoke...
nuhertz tutorial
do you have simulated your circuits?
if your circuit show oscillating, it means there is feedbacking. you must cut the feedbacking route.
then you can get what you want.
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