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Recent content by liushangpiao

  1. L

    Sparameter simulation for Verilog-AMS?

    hello,everybody.. May i make a S parameter simulation for Verilog-AMS? thanks in advance!
  2. L

    Veriloga assignment - request for verification

    Help ! about veriloga hello,everybody.. In verilogA ,may i make an assignment like this OUT[3:0]={2{1},2{0}}, thanks!
  3. L

    What is main difference when C is attached to VDD rather than VSS?

    I have met similar problem as mentioned in my project. What is main difference when C is attached to VDD rather than VSS? Any advice is appriciated. regards
  4. L

    Four questions about bandgap circuit design

    Re: Bandgap Problem!! Thanks again. Your advices are very useful for me..
  5. L

    Four questions about bandgap circuit design

    Re: Bandgap Problem!! Thanks very much for your kindness... I believe I have understaned these questions.... thanks again..
  6. L

    comparison of two LDO structures !!

    I believe I get to the bottom of this problem... Appreciate your kidness very much!
  7. L

    What is the output voltage??

    Hi,all I am a novice in analog design field, now I have a question about a circuit in Fig below. .The supply voltage is 3.3v,and w/l of all transistors is 20u/2u , Then what is the output voltage ? Thanks very much in advance.
  8. L

    comparison of two LDO structures !!

    Hi,all I am designing a LDO with required output voltage of 3V and current ability of 50mA. There are two structure to choose , but i don't know what merit each has. what difference are between them,and which is better? Thanks in advance.
  9. L

    Problem in a ring VCO with cascode biasing

    Hi.all. I am designing a ring VCO ( 3 invertors ) with cascode biasing. I get the work frequency Fo=Ibias/(k*Vpp),k is a constant,Vpp is the output swing.Obviously ,the Fo relates to the Vpp,then I think in this case the amplitude modulation (also say AM-FM) is introduced,which will influence...
  10. L

    Four questions about bandgap circuit design

    Hi,everybody! I have some problems about BANDGAP circuit design here. Those are below: 1、The ration of the two transistor area is usually 8 ,not 4 ,16 ,why? 2、Why is the temperature coefficient of Vbe -1.5mv/k to -2.3mv/k?; what is it related to? 3、what type of BJT is ususlly...
  11. L

    help :VCO jitter simulation!

    how to add the noise sources for VCO jitter simulation? i did it as follow for the power(VDD) noise source : VPDD VDD VSS sin(1.8v 0.1v 20000k). is it right? anyone answer it for me?thx very much!
  12. L

    HELP:VCO start problem

    thank u all the same. but .i can't open the webs...
  13. L

    HELP:VCO start problem

    Hi,everyone, my vco using 3-order CSL cell,single input, does not start, i knwo the A0 of a cell must be larger than 2,but i can never get it.And the problem is what is the input of a cell biased to get the A0>=2? The input nmos is in saturated region,then gm is very small ,how to get A0>2...
  14. L

    Question about Vcont value in VCO design

    Re: VCO design thank your replies... I meant that i am doing the VCO design alone ,not to do PFD ,CP and LPF,under the condition of supply power 1.8v and .18um process. Then the Vcont comes from the former part CP,and what is it? I assign it with a range of 0.3v to 1.5v,it can be gotten from...
  15. L

    Question about Vcont value in VCO design

    hi,everybody, I want to ask that the control voltage Vcont from the loop filter may vary 0 to supply voltage AVDD? In general how much is it? thx
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