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Recent content by littlefield

  1. L

    AND gate clock gatinig check

    clk2 is generated from clk1, so they are not ASYNC. ---------- Post added at 02:04 ---------- Previous post was at 01:57 ---------- if the gating cell is ICG or latch based clock gating cell, what you said is correct; however, i use the ADN gate, so it should check from A to A for setup.
  2. L

    AND gate clock gatinig check

    In my design, I use an AND gate worked as a clock gating cell, this is the RTL simulation result of this circuit. __A________________ B _______ C_______ D _____ time __|￣￣|____|￣￣|____|￣￣|____|￣￣|____|￣￣ clk1 __|￣￣￣￣￣￣￣￣￣￣￣￣￣￣￣￣|____________ enable __|￣￣￣￣￣￣￣￣￣￣ | ________________ |￣￣...
  3. L

    why we don'r recommend use tri-state in the ic ??

    POWER?? WHY??
  4. L

    two clock, how to find out which frequency is higher?

    is register output or combination output? if register output,which clock should i choose? if combination output, it have glitch
  5. L

    two clock, how to find out which frequency is higher?

    two clock,one is clocka, the other is clockb i don't know the frequency of them if the frequency of clocka is higher than that of clockb, output is '1' how to implement it in verilog?
  6. L

    Why does CMOS technology dominate in VLSI manufacturing?

    Why does CMOS technology dominate in VLSI manufacturing?
  7. L

    How to swap the content of the memory cells?

    Your system has 2 memory cells and ALU. The ALU can only perform XOR operation. How to swap the content of the memory cells?
  8. L

    How to set a second bit of the register ?

    A small computer has an 8 bit CPU and only one register. XOR - is the only assembly command it understands. How to set a second bit of the register ? The initial state of the register is unknown.
  9. L

    what factors define the min frequency of the circuit?

    what factors define the min frequency of the circuit?
  10. L

    how to tranfer a pulse from a clock domain to another clock?

    how to tranfer a pulse from a clock domain to another clock domain? the frequence of both clocks are not define and can't use fifo.
  11. L

    does this circuit have problem in DFT? how to solve??

    does this circuit have problem in DFT? how to solve??
  12. L

    which input has faster response for output rising edge????

    the transistor level schematic of a cmos 2 input AND gate, which input has faster response for output rising edge????
  13. L

    the ration of channel width of PMOS and NMOS???

    To design a CMOS invertor with balance rise and fall time, please define the ration of channel width of PMOS and NMOS and explain?
  14. L

    Can this circuit work as a non-inverting buffer?

    Can this circuit work as a non-inverting buffer?
  15. L

    which of the follow circuits can generate glitch free gated_

    Re: which of the follow circuits can generate glitch free ga ____------____------____------____------____clk ------____------____------____------____------~clk ___________________-----------------------en ___________________x___------____------gate_clk if...
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