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Re: Dummy structure
Layout guys will not add dummy themselves. They all depend on designer to tell them. In current process, removing a dummy will not save much areas. Why not?
arun layout techniques
Read the design rule or design manual before sending your chip for fabrication. Last time, we miss the antena rule and did not check it. lots of chips failed.
Think of small signal as the derivative at one point of the curve and the large signal as the shortcut of two ends of the curve. When calculating the small signal behavior, the circuit is linearized at the DC point.
You can build a ideal voltage controlled capacitor model using Spectre verilog or Verilog A, and then just change the control voltage during simulation. it is very simple. But you need to use spectre.
I think the precision depends on how to model your PLL. If you can model it precisely, behavior simulation result could be close to your circuit simulation result. First, you can build your part with Spectre Verilog, then replace then with real circuit and run simulation with spectreRF.
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