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Under this article using xilinx FPGA , a process is only to implement a upsample factor of 4 ,a 16 FIR filter coefficients are used, so what if a upsamle factor is 10 , is it need to use 100 fir filter coefficients ?
In the given diagram the near IC IR2148 MOSFET is IRFP4321 and the bias resistor is 6 OHM . If i replace these two MOSFET with IRFP460 , what should be the resistor value ? can someone give me the answer ?
I wish to use 8052 to display ks0108 glcd , also wish to display char in effect of shift left style like calculator when pressing key , I search the web but no result is found , can someone give me some hits ?
I found a web site gives pwm generator with multiple phases output ,however it is supposed the pwm frequency is given , what should I modify the code so that any pwm frequency can input to the vhdl code ...
I have a impulse response in the form h(n) = sin(pi(n-0.15))/(pi(n - 0.15)) , this impulse response can be truncated, windowed, and delayed , truncate just multiple with window function , the problem is how many delay should be used ? Is there any formula ?
I decide to use 4 250MSps adc interleave to 1000MSps and connected to Spartan 3 fpga for processing, so I wonder can spartan 3 internal block can withstand this 1 G Hz frequency ?
There is a demo emwin file using microchip pic32mz chip , under the file I can amend the vertical sync , horizontal sync etc , but I cannot find out how to set pixel clock of tft lcd , are there anyone who have this problems ?
I have five verilog IP file in Quartus NIOS II format , and wish change them to in Xilinx IP format , the most difficult part is lcd_buffer.v which is involved in Avalon part , As I am not familiar with Xilinx , can someone help me change them to Xilinx format ...
In a three stage cic filter and the decimation factor is 32 , does it means that overall decimation is 32*32*32 ( 32768 )or just 32 only?
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I search the google found it only 32. For dso in fixed 100MHz sampling clock to adc , can I achieve lower the sampling rate like...
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