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Ok, I did some more research and settled on the FSMD "template" used in the book FPGA Prototyping By Verilog Examples by Pong P. Chu (I highly recommend this book to anyone learning FPGA design; there is a VHDL version as well). It uses current and next registers for everything, which I wanted...
@FSM, thanks for the advice. I got the template from various examples I found Googling... I might have "Frankenstein'ed" them into the monster I have now. ;) I'll rework the FSM to directly assign to state without using next_state (I feel more comfortable doing it that way anyway). As for...
I've written a FSM to take a 14-bit binary number (decimal 0-9999) and convert it to 16-bit BCD using the following algorithm:
1. Shift the binary number left one bit.
2. If 14 shifts have taken place, stop.
3. If the binary value in any of the BCD columns (units, tens, hundreds, thousands) is...
Not yet, but I'm getting close. I played with it a bunch tonight and thought I had what should work, but I'm getting slightly different values back from the addresses I wrote to (async). The upper byte is correct, but the lower byte is wrong. I think there's a signal I have to toggle for a...
@mrflibble: That EDK Project may have been something I ran across before after all. It's c code that compiles down to code that runs on MicroBlaze, and seems to not have much code in the zip file at all. Mainly calls library routines (like XUtil_MemoryTest32) that I assume come from some...
@rberek: That's been a major help to me throughout this whole experience; that and the **broken link removed** document from the documents tab on that same page. I think I understand from a higher level WHAT I need to do (thanks to those verilog files and that pdf), just not quite HOW to do it...
Ok, I'm going to do something I don't normally do. I'm admitting defeat. I've spent over a week now trying to figure this PSRam access out and it's simply eluding me. Can someone that has a Nexys 3 (or Nexys 2) please throw together a simple synthesizable demo using the switches/buttons as...
I've been reading the Micron **broken link removed** on their MT45W8MW16 70ns PSRAM over and over and over, searching Google for any type of examples, making TONS of notes, and I'm going cross-eyed trying to understand it fully. It should be fairly simple to do synchronous read/write from/to...
I just sent a request for a quote to X-Tek for their X-HDL software. I'm assuming that since they don't list the price on the website, it's probably pretty expensive. But I'm curious, so we'll see. When I get the quote I'll post here so we can all have a idea of the cost.
I just realized the asynchronous mode of the PSRam is reading/writing 16 bits at a time, so I'm getting 2 bytes at a time. So If I read 2 bytes (2 pixels @ 8-bits each) every other clock cycle of my 25MHz clock (12.5 MHz), I can read the data fast enough to update the screen from it. Not sure...
I forgot to post the code I have working for asynchronous PSRam access, just so anyone else looking for how to do this can run across it in the future. :) Also, I welcome any comments (positive or negative).
psram_test.v
module psram_test
(
input wire clk,
output wire [7:0] Led...
I'm trying to learn how to write and read the cellular ram (PSRam) on the Nexys 3 board. I've read the Nexys 3 Reference Manual, did a TON of Google searching (learned what PSRam was and probably about 7 or 8 other new terms), and finally managed to find some sample Verilog code and...
Ah, optimizations! I don't know why I didn't think of that. I "grew up" in the c programming world and was (decades ago) very familiar with the software equivalent, compiler optimizations. The thought that "synthesis" optimizations could be occurring never occurred to me. Thanks for that tip...
Have you had a chance to try synthesizing the project yet? I'm really just curious to know if the problem is something with my environment or the code itself. I've done several (small) projects since then and they've worked fine, so I have to assume it's something with the code, but I'm just...
I've tried replacing all my source files with the source files from the book's website (fp_adder_test.vs, fp_adder.v, hex_to_sseg.v, and disp_mux.v), with the exception of the .ucf file (the one from the book is for a Spartan-3 board, I'm using a Nexys-3 w/Spartan-6) and still get the same...
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