Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by laserist

  1. L

    Value of the RFC in a bias circuit.

    Generally there is a rule of thumb that the impedance of the RFC is at least ten times higher than the impedance can be seen from this node without RFC. But i prefer to choose as large as i can. The impedance of an inductance is jwL. Take wL ten times larger than the input impedance.
  2. L

    Multiharmonic load termination vs class F

    I think there is no solid difference between these terms. But Class F can be made by only third harmonic termination. Multiharmonic has a wider meaning
  3. L

    How to enlarge the SlewRate of a amp as possible as we can?

    Re: How to enlarge the SlewRate of a amp as possible as we c Maybe as a choice; if you don't have any restrictions, you can try to bias your circuit for a higher DC current so you can charge/discharge your capacitances faster.
  4. L

    Question about LNA and out-of-band rejection filter

    Re: LNA Question To give this kind of spec at dB form is not sufficient. I think the best way of express is give it at dBc form. Ex: "25 dBc @ 50 MHz of 1575.42 MHz" This means at +/- 50 MHz of 1575.42 the signal must be 25 dB lower than the desired signal. So VSWR is right.
  5. L

    Who has papers about Lateral PNP in p-sub CMOS Process?

    In p-sub processes, lateral PNP transistors are generally not good transistors.They have small beta(less than 20-30) and processes generally don't guarantee reliability. I use lateral PNP's in a bandgap circuit which there is no need to amplify any signals and I encounter some problems about...

Part and Inventory Search

Back
Top