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Hello guys,
I have a synthesized netlist at 1GHz (STA does not report any violation). However, when I am simulating the netlist (at 1GHz) I am getting: Warning! Timing Violation.
I think there is a problem in my testbench, but I am not able to figure it out.
The testbench used is the following...
Hi,
I would like to estimate the power consumption of my ASIC design at each clock cycle.
At the moment I have set up the following flow:
1) Generate the netlist using RTL compiler.
2) Dump the VCD file using NC-sim and the netlist obtained at step 1.
3) Back in RTL compiler, for each clock...
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