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Thank you Shobhitk for your efforts. I have attached a pdf with this post. It contains a few digital design problems often asked in interviews. Please note that it contains questions only.
Greetings colleagues,
I am currently working on the Synopsys Low Power Flow Workshop (Lab 3 Synthesis). The library files used in this design are :
1) saed90nm_hvt_rdsr.db
2) saed90nm_lvt_rdsr.db
3) saed90nm_max_hth_hvt_rdsr.db
4) saed90nm_max_hth_lvt_rdsr.db
I have specified the operating...
Signal Electromigration results from an increase in current density caused by the use of smaller line widths and higher operational speeds in IC Designs. It can lead to shorts or opens due to metal ion displacement caused by the flow of electrons.
Resolving EM violations:
1. Load signal EM...
Lets say you want to find out the delay of a gate :
The delay of a gate consists of two components. One is the parasitic delay p (intrinsic delay of the gate and can be found out by considering the gate driving no load) and the other component is the stage effort f.
Hence the delay d = f + p...
You can try out the examples in the book : FPGA Prototyping by Verilog Examples (Pong P Chu) It covers every aspect of Verilog and Digital Design and is the best book for beginners IMHO.
For your query regarding 'define and parameter, go through this thread : https://www.edaboard.com/threads/72802/
Constant Propagation :
Constant propagation is a very effective technique for area minimization,since it forces the synthesis tools to optimize the logic in both forward and...
Check out this link to know the basics of the complete PD flow :
**broken link removed**
IMO, the best way to learn about the flow is to refer the Synopsys ICC Manual.
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