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For 8 ghz input and 3.65 first LO we will have. 4.35 Ghz IF and products located at 7.3, 3.65 and 0.7 Ghz and some spurs. After filtering we have the 4.35 Ghz IF. Mixing it again with the LO will give you the 700 Mhz result and products at 4.35, 3.65 Ghz.
For this case you are correct. But for cases like a 8-8.4 Ghz to 700 Mhz converter, you can have a 3.65-3.85 Ghz oscillator and use it in both mixing stages.
I was wondering why frequency converters use 2 mixing stages (and 2 different oscillators). Why not use the same oscillator for both the mixing stages. Is it the phase noise or the step size issue?
Thank you in advance.
Dear All,
I've found several logic gates (AND,XOR) accepting >3 Ghz input frequency, However I am not sure if there are Schmitt triggers supporting >2 Ghz input frequency. The only parameter I've found in datasheets is Propagation delay in nsec.
Please help.
We Investigated some differential clock drivers, buffers. Their problem was the duty cycle of the inverted output. For a %50 duty cyle, the output can vary between %45 to %55 which is an unwanted feature.
Thanks for the answer, we are aware of adding/removing 7.5 cm transmission line to get the required phase shift.
The problem is 7.5 cm is a lot on the PCB and the error in the desired phase cannot be minimized by this method.
Is there an alternative method? We checked out the Minicircuit device...
Hi All,
We have a QPSK modulated signal 700 Mhz IF, 80Mhz BW to demodulate.The bit rate is 100 Mbit, roll-off is 0.65.
Now we have to select an RF-ADC,FPGA board to demodulate it.
The RF part can be handled by an I&Q demodulator circuit.
Our question is; what should be the minimum sampling...
Dear All,
I have a 100kbps BPSK modulated signal at 1 Ghz.
Usually one downconverts (Oscillator+Mixer) the signal and recovers the Data and Clock using an ADC and DSP.
Since we have a BPSK signal can't we just detect the phase changes and filter out the transmitted 100kbps signal? No...
Dear All,
I remember reading a demodulation method by an egyptian inventor. Unfortunately I do not remember the name of the method which was the same as the Egyptian inventors name.
Hi All,
I have a 70 Mhz IF, 2Mhz BW, QPSK modulated signal to demodulate.
Should I use a Digital Down Converter (DDC) to get the I-Q pair or should I use a downconverter to get Zero-IF as an input to ADC.
Which one is better?
Also for a 720 Mhz IF, 100Mhz BW, QPSK modulated signal which...
Hi All,
I have designed a PLL with a 10 MHz Reference and a 2.2-2.6 GHz VCO (using discrete PFD and Frequency divider). I wonder if can improve the phase noise/spurious by placing a 10 MHz Crystal filter in front of the feedback loop. For a divider value of 220 we get 2200 Mhz /200 =10 Mhz...
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