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Hi,
Generaly, you should use couple of upper metal layers (but not the highest, as the highest layers are used for Power wire structures, such as Rings and Stripes) due to small resistance thay have (low R parasicits)
Hi,
I am afraid, you should use dfII extracted view for VAVO. One of Cadence AMS Kit (release >= 6.1.2) chapters focused on Ultrasim-VAVO methodology usage
Hi,
It is exectly what I meant. Actially it depends on SOC Encounter release version as 7.1v and earlier releases supported 'fixTranViolation' command also
Re: Q on csh script
Hi,
I see. It looks like the perl script is waiting for some STD INPUT
Pay attention that you try to evaluate the perl script result. I suppose that process would like user to type something, to say another words it wait for response from input stream STDIN. Debug this part...
Re: Q on csh script
Hi,
Yes, sure you can run tcsh script in csh script. Just make sure "tcsh" script is "executable" OR you can use following statment to run "nonexecutable" script:
hi iwpia50s,
Actually above timimg constraints (clock root is defined at PLL output or MUX output) are fully acceptable for BE (I use this flow often. I use Cadence Encounter BE tool set).You can easy fix the slew BEFORE the mux through max_transition constraint usage.
hi laughlatest,
clock...
It affects to clock latency. And it is your choise and it depends on your design. U should understand how clock latency value affects on I2C and C2O cost groups.
I am just wonder you will get over-optimistic clock tree latency for BE design (propagation clock latency) if you point the clock tree...
Hi,
I do not know about Synopsis flow, but you should use set_clock_latency instead of input_delay for clock in Encounter based flow.
The next question is "what place is the clock root?". The answer depends on chosen archirecture. Do you cotstraint any output pins? I mean, have you any...
Re: clock transition time vs setup/hold time of a DFF
Hi,
The answer is yes, of cause, setup time depends on clock transition time. You can see it in detailed STA tool's LOG as some additional to path delay. Besides, you can see it in liberty file:
And, mostly important: look at DFF schematic...
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