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Hi,
If u don't have any timing violation then for post layout simulation better dump the "SPEF" file and used for simulation and u will better results than SDF.
Regards,
Prashant
nand diesize
Hi,
i totally agreed with usrlen description and if u want to calculate mathematically then go through ASIC text book by M. Smith, Chapter no.15 and he has explained very clearly about "Die Size".
Prashant
Hi,
if u r using Encounter tool then u search workshop lab in encounter doc then u will find three docs(in pdf format and preferably in DTMF folder), go through it and use it or do it. let me know if u have any problem.
Prashant
Hi siva,
u first check all the inputs which u import in SoC Encounter and check in the flow where exactly u have to do timing analysis.
In timing analysis for what (is it for setup or hold) and this is all for Encounter tool not for PKS.
u clearly mention where exactly u r doing timing analysis...
Hi,
it depends on the requirements of the projects.
Synopsys : Prime Time
cadence : Common Time Engine (CTE)
Magma : Blast fusion (not sure)
I worked on CTE and it is one of the best tool but still Prime Time is used by all company.
Prashant
Hi Siva,
Arvind has given correct solution and one more thing u can try if possible,
there is a command by name "ctlf" by which u can convert "tlfs".
prashant
index of soc encounter
Hi,
u check when u inserting buffers, it will ask which r the buffers to be added then accoding to ur usage u can select the name of the buffer.
Prashant
io ＆ core pad
Hi all,
how to place IO PADS using P&R tool in ASIC Design?
In my gatelevel netlist IO PADS information is not present so is it necessery that gatelevel netlist should contain IO PADS information? if yes what r parameters to be given while doing RTL synthesis in ASIC flow.
prashant
Hi,
The parameters which u r described that all comes from the front end (After completion of successful synthesis then they will generate constraints file called timing constraint file[.sdc format] which consist the all parameters mentioned by u).
The "sroute" we have to do before clock...
Hi,
it depends on the tools capacity. if u r using Cadence SoC Encounter or Cadence Nanoroute, tool will detect the crosstalk violation and repair it and if u want see violations using violation browser.
prashant
Hi all,
I am working on flooorplaning & powerplanning using SoC Encounter tool.
in powerplanning how to generate I/O PADS and when these i/o pads r required(does this i/o pads required when anlog block is present in the design) and what basis i have to choose number of power stripe & rings.
plz...
Re: P&R with only "LEF" file and NO "LIB&
HI,
can u tell in detail about exact the meaning of "library preparation", because wiithout timing library (.lib from synopsis, .tlf from artisan) P & R tool will not work and library preparation for .LEF file.
Prashant
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