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if the delay (as specified in the SDF) is greater than the clock period, then the signal changes will not propagate through the cells/nets
you can try to simulate using a lower clock frequency
In DC, try the following after elaborate/read_verilog/read_vhdl (no compile)
1. sizeof_collection [all_registers]
2. sizeof_collection [get_cells -hier *_reg*]
you can use either design compiler (DC) or primetime (PT)
in your synthesis script, write a ddc format netlist (so that the constraints are embedded in the ddc file)
once you're done with synthesis and generated the ddc file, read it into either DC or PT. then do a report_timing -nworst 10...
during netlist simulation with SDF, all timing checks are enabled for all FFs except for the 1st FF of the synchronizer (VCS has this feature)
the goal is to check if the data bus crossing do not violate setup/hold timing (i.e. the synchronized control signal properly gates the data to the...
i think the most straightforward way is through gate level simulation with SDF, where the clocks are sweeped/skewed with each other
the first stage of each double FF synchronizer is ignored for timing checks
No =)
another way to code this is change the last case as the default case.
case(state)
2'd00 : y<=a;
2'd01 : y<=b;
2'd10 : y<=c;
default : y<=d;
endcase
this way you'll still
- pass syntax checker tools such as Leda or Spyglass (which require a 'default')
- prevent unhit lines during code...
I think STA for pre-CTS netlist is the same for both DC and PT. You should be able to use the same scripts specially for newer DC version
For post-CTS, post-routed netlist, I think you must use PrimeTime specially for clock tree analysis and on-chip-variation timing analysis
Just in case you encounter another loop =)
What I do is do a report_timing -loop before compile (after elaborate and reading the constraints). The cells in the report are unmapped and their names are closer to the original RTL.
It's hard to trace in a mapped netlist specially if DC ungroups...
I think doing either set_case_analysis or set_dont_touch_network have some possible issues
1. If with set_case_analysis, there may be some unwanted optimization in the fanout of the "master control signal". If it's really static, why not change it to a constant
2. If with...
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