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Hi all,
I am designing 1kb array of SRAM. Can anybody suggest me which type of decoder I should use? I mean to say whether to use cascaded tree decoder or ANDed decoder? Which one will work faster? can you provide MOS based schematic of decoder?
Thanx in advance...
Hi all, I want to implement analog 5 to 32 decoder in cadence virtuoso schematic editor. I have made 5 to 32 decoder using one 2-4 decoder and four 3-8 decoders. But at the time of simulation, I am getting an error saying that "some branches form rigid loops when connected to circuit"... I have...
Hi all, I want to perform post layout simulation of sram cell in cadence 6.1.4. I have completed drc n lvs steps successfully with assura.But i can't extract parasitics...It gives error that "no directory found". I have attached screenshots of settings for directory name...so please help me if...
Hello everybody, I'm making design of SRAM cell in cadence 6.1.4 I have generated layout in virtuoso layout editor but i dont know how to calculate the area of layout... Can anybody help me?..Thanx in advance...
Hi all, I am using cadence 6.1.4 and i can't find the option of parametric analysis from ADE window... In ADE window, from tools menu, i just found only 4 options...calculator, result browser, job monitor and dcm... so please anybody show me the proper path to perform parametric analysis?
yeah exactly. After that I have already tried pass transistor and i got the desired outputs...
but can you please tell me from which waveform I should measure the read delay? I mean to say from bit lines or from q and q_bar points? I have attached my waveforms here...Between 5 ns and 6 ns, when...
Hello, thanks a lot for answer. I have solved the problem in writing operation. But now i am facing problem in reading operation. Actually i want to measure delay in read operation. so can you please help me in completing the read circuit??? I want to disconnect the data lines from cell while...
Hi everybody, i'm making analog design of 6t SRAM cell in cadence. but my cell does not store the value 0 or 1 inside the cell. when i apply complementry values to bit line (Vdd) and bit_bar (gnd) line it keeps the value storing inside bt as i remove the voltage it takes the value of power...
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