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Hi,
FPGA would be a very good option for prototyping ASIC functionality w.r.t logic verification, but for power performance it doesn't give you any valueble information, becuase of the technology differences of FPGA to ASIC and differnce in the kind of cells logic cells used in ASIC and FPGA
Hi.
If these two always blocks are considered sseperately for the behaviour analysis, then both doesn't have any difference w.r.t simulation. But for synthesis using blocking statement for modelling a flop/register element is not a good coding practice.
If we put these two statements in the...
I don't expect DC/PT to find the false paths for my design.
My query is if I specify the false paths for the synthesis in my constraints, can I use the DC to report paths in the netlist, that are specified as false paths in the constraints input file to DC?
Hi All,
I have done Asic-synthesis of mys using DC and STA using PT. I have specified all paths between clock-domians as fasle paths.
For my Gatelevel simulation with SDF back-annotation I'm seeing violations on signals crossing the clock domains.
If I get the complete false_path for my...
wire and reg difference in verilog
Here is one more difference between wire and reg come from the simulation point of view.
The value of wire(0on R.H.S) is evaluated for every simulation delta/ change in simulation time, where as the reg is evaluated only when there is change in any of the...
asic false-path
Marc,
w.r.t EDA tolls in your reply you mean to say that, adding false/multi-cycle paths will make the tools run slower. If yes please justify that?
Hi omara,
You need to have a reset in ur case also.
What will be the initial output of the counter if you do not assert reset...
Regards,
RamaMohan Rao K
false path
Hi,
As per my experience i feel synthesis tool might not give out any multi-cycle/false paths.
We need to identify the multi-cycle and false paths, as per design and specify them to tool.
Generally paths crossing clock domains are specified as false paths to the tool so that the will...
Hi,
Pls guide me to find the following for a verilog module take using Xilinx ISE and modelsim simulator.
1. CPU time taken
2. Memory used for simulation
thanks in advance,
Ram
Hi anyone pls help me how to open a .tiff file in XP OS.
When I open with Microsoft office document imaging, a blank page is getting opened.
Pls guide me ASAP.
Thanks in advance,
Ram
Can anyone explain me about the significance of VCD files for power analysis in Xilinx environment?And exactly how do we do the power estimation of the design using VCD files.
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