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Recent content by kolla

  1. K

    Interview question - Need Your opinion

    Thanks gck for the explanation.. Would you show me how the connections should be made.. A drawing or a picture would help a lot.. Added after 55 minutes: Actually I think I figured it out... Looks like something like this'd work. What do u think? **broken link removed**
  2. K

    Interview question - Need Your opinion

    This is an interview question I found and I'm looking for your feedback.. (There was no answer given) Q: How do you convert transparent D-latch into rising edge D-Flop? My initial thinking was to simply add a clock to do this. But maybe the question is asking something deeper?? Would you guys...
  3. K

    convert a FF with a reset to a flop with a set

    reset vs set What's the easiest way we can convert a FF with a reset to a flop with a set? Can someone explain..
  4. K

    SOC Encounter question

    Thanks again cop02ia for the great answer. Your experience was indeed helpful to expand my knowledge here. I heard the SOCE has an integrated "Analog" router which apparently is intended to be used with mixed signal designs. But since SOCE is a digital platform I wonder how this is used in...
  5. K

    Adding IOs in SOC Encounter

    addring encounter my understanding is that you have to add the IO fillers via a command prior to routing. sroute will connect the power rings to the power pads, fix unconnected stripes and also connect std cell power pins to global power lines.
  6. K

    Help explain FPGA IP vs ASIC IP cores

    I meant design an SOC :D Thanks guys for your feedback.
  7. K

    SOC Encounter question

    Thanks cop02ia ! very helpful answer again. Are you familiar with SOC Encounter? Does it allow building an SOC with both Analog & Digital hard macros? If so how does SOCE helps marry these A & D blocks into an SOC? (any specific features or methods in SOCE) These are some of the answers I'm...
  8. K

    SOC Encounter question

    Thanks cop02ia !! That was indeed very informative as I'm still learning these things. This makes sense now.. and I see why we can't use FPGAs on an ASIC SOC. I saw somewhere that a Hard Macro is defined as "a block generated in a methodology other than P&R". This confuses me a bit...can you...
  9. K

    SOC Encounter question

    fpga encounter Thanks kumar. So is it correct to say that all my Hard Macros that I'm bringing into SOC encounter must be ASIC blocks made for a specific process technology and they come in as gds/lef?
  10. K

    SOC Encounter question

    insert black box in soc encounter Hi friends, Can someone tell me whether Cadence SOC Encounter can be used to build SOCs with FPGA Hard Macros (IP)? If not what tool can do that? Thanks in advance
  11. K

    Help explain FPGA IP vs ASIC IP cores

    asic ip Can some kind soul explain the differences between ASIC & FPGA IPs for me? Is it possible to build an SOC using both FPGA & ASIC IP cores? If so what tool facilitates that? Any help or links to more reading is highly appreciated..
  12. K

    use of SOCE to bring in third-party IPs into a SOC design

    SOCE and IP Does anyone have details about how to use SOC Encounter to bring in third-party IPs into a SOC design? Is there a recommended flow and whether SOCE provides any tools for validating or facilitating such a flow?
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