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vertical counter logic is wrong
check this vhdl code for vga sync generation (example code from rapid prototyping of digital systems)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY VGA_SYNC IS
PORT( clock_25MHz, red, green...
calculate video fifo depth
fifo depth will depend on how frequent you read
if you read every alternate clocks then a fifo depth of 256 should be sufficient for you.
check this link to know more about fifo depth calculation
https://www.asic-world.com/tidbits/fifo_depth.html
install ise on linux
i have successfully installed ISE8.2 on slackware 11.0
run the script setup located in ise82i\platform\lin folder of the DVD
regards
kib
counter division vhdl
Why do you require a divide by 2.5 circuit.
Why not directly use a divide by 5 cicuit to get 1Hz from 5Hz.
check this
regards
kib
Re: clocks in DDR core
There are 2 ways to clock a DDR flop's
Below image shows the same
I have normally used the inverter inside the IOB to invert the clock and has worked for me without any problem. I have target tested my design upto clock speed of 166MHz.
Regards
kib[/img]
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