Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Guys, please do not confuse.
These are referring to the same...
To disable (switch off) the clock to a register, a clock gating cell is used...
To enable/disable this clock, clock enable will be used in clock gating cell...
So, both are same...
For simplicity, take an AND gate as clock...
Isolation cells are used to isolate the outputs at the output of the power domain. Power domain is a block in a design that can be switched off when it is not required.
When a specific block is switched off, the outputs of the block will have X, if this value is propagated to switched on...
rtlcompiler wireload
Hello,
I know how to create custom wireload models in DC flow but not in RTL Compiler.
Can you anyone of you please let me know the way to do it in RTL Compiler, sample script is much helpful...
Thanks,
NK
Re: Power estimation tools
Atrenta, SpyGlass has accurate Power Estimation engine. It can estimate power at RTL/Gate/Post Layout level.
They have proved their correlation against silicon very well.
Regards,
Narayana
SpyGlass is one of the best tool to catch bad verilog/vhdl coding styles.
It runs pretty fast compared to traditional implementation tools.
Regards,
Narayana
SpyGlass-Constraints product can do that, it can check on RTL as well as Gate-Level netlist. But it does not come free and will be sold to Design Companies only.
Regards,
Narayana
Re: glitch detection
I guess Clock_glitch04 rule in SpyGlass should be able to catch such situation, they have other glitch catching rules as well. These rules are part of SpyGlass-CDC.
Regards,
Narayana
Re: Help me SpyGlass
You need to register in their website, then you would be able to download software/manuals from their website.
They have 24 hrs support, so you can get answers faster.
They have solutions for all sort of problems in RTL like Power, Timing Constraints, DFT and CDC.
I...
Guys,
I know how to dump vcd in general, but I was not able to dump 2-d arrays in the vcd file.
For example, in my verilog module, if I have a memory reg [3:0] mem [3:0].
Now, can you please let me know, how should I refer them in testbench. And also, what do I need to do to dump these...
Re: DC issue
May be you can give design directory in the search path, so that DC will search for the include files in the design directory as they are located there.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
