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Recent content by khorramrouz

  1. K

    output impedance simulation

    thanks for reply If i apply an input signal which fulfill small signal assumption,why the output impedance derived from (V2-V1)/(I2-I1)differ from one extracted from ac analysis? I have done a test with ideal current source parallel with a resistor and capacitor (as output impedance) .the output...
  2. K

    output impedance simulation

    Dear FvM i put a capacitor series with ac voltage source and the results became the same. As i explained in 2, i tried to calculate the output impedance by simulation and by transient analysis.why the results differ? i want to know if ac analysis in this case is usable?which analysis can result...
  3. K

    output impedance simulation

    thanks for your favor i grounded input signal and applied an ac source at ouput node and did an AC simulation in cadence (frequency analysis)
  4. K

    output impedance simulation

    Hi all I designed an op-amp for an improved Howland current source and want to plot it,s output impedance.I applied an ac voltage source with Vac=1V at output and measured output current and then plot V/I , also with applying I=1A, the output impedance will be V.(with grounding input) 1- But...
  5. K

    Maximum supply voltage for nmos2V andnmos3v in tsmc18rf?

    Hi All I,m using Tsmci8rf and there some nmos and pmos in the component list. How can i know the specification of each one? Does 2V and 3V refer to maximum voltage which can be used? best regard
  6. K

    DC voltage rejection?

    Dear friend the question is about an folded cascode OTA with single ended output.to have good swing i designed the circuit and set Vbias and W/L ratio. Vdd=1 v and Vss=-1v. under this condition a dc voltage (407 mv) seen at output node which eleminates the + swing. so i want to know : 1-how...
  7. K

    DC voltage rejection?

    although i change Vgs and W/L ratio, when i set the input to zero, a dc voltage is seen at output node. how can i reject this and what is it,s reason? thanks for your help
  8. K

    How remove DC in output?

    yes the output node voltage should be zero but in my design with vdd=1 and vss=-1 , the dc voltage is 416mv and possitive swing will be cuted n IC design i think use of capacitor effects on size and freq. respons
  9. K

    How remove DC in output?

    Hi All I designed an OTA which called Recycling folded cascode.a Dc voltage in output nodes degrades the swing.as i use a dual power i want the Dc be Zero. thanks for yiur idea
  10. K

    problem with cadence

    Hi all i have designed an Ic with nmos2v & pmos2v. it,s output swing is very low plz answer this qestions: 1-the max. supply voltage ? 2-how can i add another mosfet to my software? best regards

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