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Recent content by KHDAK

  1. K

    How to avoid unwanted logic removal during synthesis?

    Re: How to avoid unwanted logic removal during synthesis Thanks englishdogg! As it turns out synthesizer had renamed/grouped some of the registers hence it is not possible to locate them in Netlist. So I am now saving the results to external memory where I can easily check them.
  2. K

    How to avoid unwanted logic removal during synthesis?

    Re: How to avoid unwanted logic removal during synthesis Thanks for the reply permute! Yes I am sure I am using the right files as the Netlist with looser timing constraint is also built from the same files. Is there a command in RTL compiler for "Retaining Hierarchy" as there is in Xilinx ISE ?
  3. K

    How to avoid unwanted logic removal during synthesis?

    Hi All, I am synthesizing a processor design with Cadence RTL compiler. The synthesized netlist works fine (in simulation) and contains all necessary logic when I set a loose clock constraint (5000ps). But when I synthesized the same files with a tighter clock constraint (1800- 3000ps) the RTL...
  4. K

    setup delay in Xilinx ISE post P&R Simulation model

    Hi, No there is no other signal connected to that FF. It works fine If I pulled global reset active for 100ns in my testbench at the start of simulation.
  5. K

    setup delay in Xilinx ISE post P&R Simulation model

    I have re-labeled the waveform. A guy from Xilinx forum says it is an internal reset delay which is exerted upon configuration. https://obrazki.elektroda.pl/8398369200_1371032469.jpg
  6. K

    setup delay in Xilinx ISE post P&R Simulation model

    Hi, Yes, the waveform shows the output of a FF from timing simulation file. My simulation works fine when I set initial reset delay of 100ns or more, In my behavioral simulation the delay was set to 10ns, but now in post P&R timing simulation my design don't work correctly with this value.
  7. K

    setup delay in Xilinx ISE post P&R Simulation model

    Hi All, I am using modelSim to simulate post P&R simulation model of a processor design generated by Xilinx ISE 13.2 (ABC_timesim.vhd). It appears that there is a setup delay of 100ns in the model and the FF defined in it only start working after that time. Is this delay really part of...
  8. K

    Synthesis of RAM in Cadence RTL

    Thanks rca :)
  9. K

    Synthesis of RAM in Cadence RTL

    ok but I am getting a message that RAM component is inferred as a logic abstract and I also can't see that logic inside RAM block in schematic view.
  10. K

    Synthesis of RAM in Cadence RTL

    Hi, I have technology library for 2048x32 RAM and I want to use it with my VHDL design in Cadence RTL compiler. This library contains *.lib flies and VHDL simulation model. When I include this RAM as a component in my VHDL code the RTL compiler interpret it as a black box. Do I need a VHDL file...
  11. K

    RAM generation from CORE GEN 13.2 (Block Memory Generator 6.2)

    Thanks r.b
  12. K

    RAM generation from CORE GEN 13.2 (Block Memory Generator 6.2)

    Hi, I want to use a single port 32kb RAM in Virtex 5 FPGA. I obtained attached VHDL file from CORE GENERATOR in ipcore_dir folder, this file is a simulation model of the RAM. My question is, Where should I look for actual implementation file for this generated RAM, which can be synthesized with...
  13. K

    [SOLVED] Cadence Encounter - Synthesis faild due to Latch cell

    The error disappears after adding "lib_search_path" attribute. Thanks rca
  14. K

    [SOLVED] Cadence Encounter - Synthesis faild due to Latch cell

    Thanks rca, It says "instance switch_reg[0] requires a simple latch : check the libraries for necessary latch cell, the cell could be marked unusable" I think latch cells are not included in the library I am using "CORX9GPHS_Nom.lib".
  15. K

    [SOLVED] Cadence Encounter - Synthesis faild due to Latch cell

    Hi, I am trying to synthesize a FPGA based design with Cadence RTL compiler to find out the performance difference with ASIC implementation. The elaboration phase works fine but when I try to synthesize "synthesize -to_mapped" I got an error message saying "unable to map design without a...
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