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*.seedprom
There is "*SEEDPROM" in the subcircuit of layout extracted netlist after LVS and some transistor is exist in the upper level cell.
What's the problem? Layout problem?
Before designing 512K memory design, I have a problem during design 8bit memory.
I am doing layout with Cadence Virtuoso. I had done layout 1bit cell first. And made 2bit cell with 2 instance of 1bit cell, 4bitcell with 2 2bitcell and 8bitcell with 2 4bitcell.
Finally, doing LVS with...
There is a question about layout. I am designing SRAM in 0.18 CMOS process.
Someone told me that there is a technique - drived mask - and it's possible to make nmos using only "ndiff" and poly except "n-implant".
Is it right? If so, what's the method?
i think that hspice is better in terms of accuracy also.
But spectre is faster than hspice and easy to use because it can be used interactively with cadence.
vlehelp/vlehelp.pdf
Enter 'cadence & layout' in google. There is so many tutorial in several university. In the cadence tool, there is user guide (.......VLE....) in 'doc' directory
star rcxt tutorial
After DRC, LVS with Calibre I would do RC extraction using Star-RCXT. Because of my first trial, I don't know about it.
Are there another needed file except ***.gds?
Where can I find the tutorial about RC extraction using Star-RCXT?
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